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2013-04-01Merge load/store sequences with adresses: base + index + offsetArnold Schwaighofer
We would also like to merge sequences that involve a variable index like in the example below. int index = *idx++ int i0 = c[index+0]; int i1 = c[index+1]; b[0] = i0; b[1] = i1; By extending the parsing of the base pointer to handle dags that contain a base, index, and offset we can handle examples like the one above. The dag for the code above will look something like: (load (i64 add (i64 copyfromreg %c) (i64 signextend (i8 load %index)))) (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) The code that parses the tree ignores the intermediate sign extensions. However, if there is a sign extension it needs to be on all indexes. (load (i64 add (i64 copyfromreg %c) (i64 signextend (add (i8 load %index) (i8 1)))) vs (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) radar://13536387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01Add more PPC floating-point conversion instructionsHal Finkel
The P7 and A2 have additional floating-point conversion instructions which allow a direct two-instruction sequence (plus load/store) to convert from all combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores, only some combinations were directly available). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01Fix PowerPC/cttz.ll to specify a cpu (and use FileCheck)Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01Add the PPC popcntw instructionHal Finkel
The popcntw instruction is available whenever the popcntd instruction is available, and performs a separate popcnt on the lower and upper 32-bits. Ignoring the high-order count, this can be used for the 32-bit input case (saving on the explicit zero extension otherwise required to use popcntd). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01Add support for vector data types in the LLVM interpreter.Nadav Rotem
Patch by: Veselov, Yuri <Yuri.Veselov@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01X86TTI: Add accurate costs for itofp operations, based on the actual ↵Benjamin Kramer
instruction counts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.Benjamin Kramer
A vector sext + sitofp is a lot cheaper than 8 scalar conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31Add the PPC lfiwax instructionHal Finkel
This instruction is available on modern PPC64 CPUs, and is now used to improve the SINT_TO_FP lowering (by eliminating the need for the separate sign extension instruction and decreasing the amount of needed stack space). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31Cleanup PPC(64) i32 -> float/double conversionHal Finkel
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled because it relied on broken EXTSW_32/STD_32 instruction definitions. The original intent had been to enable these 64-bit instructions to be used on CPUs that support them even in 32-bit mode. Unfortunately, this form of lying to the infrastructure was buggy (as explained in the FIXME comment) and had therefore been disabled. This re-enables this functionality, using regular DAG nodes, but only when compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead) are removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30DAGCombine: visitXOR can replace a node without returning it, bail out in ↵Benjamin Kramer
that case. Fixes the crash reported in PR15608. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30Change '@SECREL' suffix to GAS-compatible '@SECREL32'.Benjamin Kramer
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'. With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here). Patch by David Nadlinger! Differential Revision: http://llvm-reviews.chandlerc.com/D429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[NVPTX] Add NVVMReflect pass to allow compile-time selection ofJustin Holewinski
specific code paths. This allows us to write code like: if (__nvvm_reflect("FOO")) // Do something else // Do something else and compile into a library, then give "FOO" a value at kernel compile-time so the check becomes a no-op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30Implement XOR reassociation. It is based on following rules:Shuxin Yang
rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2), only useful when c1=c2 rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2)) rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2 rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2 It reduces an application's size (in terms of # of instructions) by 8.9%. Reviwed by Pete Cooper. Thanks a lot! rdar://13212115 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Add patterns for DSP indexed load instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Fix DSP instructions to have explicit accumulator register operands.Akira Hatanaka
Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Move the code which does dag-combine for multiply-add/sub nodes toAkira Hatanaka
derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Updated test0 of retain-not-declared.ll to reflect the fact that ↵Michael Gottesman
objc-arc-expand runs before objc-arc/objc-arc-contract. Specifically, objc-arc-expand will make sure that the objc_retainAutoreleasedReturnValue, objc_autoreleaseReturnValue, and ret will all have %call as an argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Exclude the X86/complex-fca.ll test at it probably wasn't supposed to work ↵Timur Iskhodzhanov
on Windows git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178375 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Add clang.arc.used to ModuleHasARC so ARC always runs if said call is ↵Michael Gottesman
present in a module. clang.arc.used is an interesting call for ARC since ObjCARCContract needs to run to remove said intrinsic to avoid a linker error (since the call does not exist). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29move testcase into appropriate X86 subdirectory.Adrian Prantl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Implement FRINT lowering on PPC using frinHal Finkel
Like nearbyint, rint can be implemented on PPC using the frin instruction. The complication comes from the fact that rint needs to set the FE_INEXACT flag when the result does not equal the input value (and frin does not do that). As a result, we use a custom inserter which, after the rounding, compares the rounded value with the original, and if they differ, explicitly sets the XX bit in the FPSCR register (which corresponds to FE_INEXACT). Once LLVM has better modeling of the floating-point environment we should be able to (often) eliminate this extra complexity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178362 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Split the llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m testcase ↵Adrian Prantl
into a CFE and LLVM part. rdar://problem/12767564 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Remove the old CodePlacementOpt pass.Benjamin Kramer
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Add PPC FP rounding instructions fri[mnpz]Hal Finkel
These instructions are available on the P5x (and later) and on the A2. They implement the standard floating-point rounding operations (floor, trunc, etc.). One caveat: frin (round to nearest) does not implement "ties to even", and so is only enabled in fast-math mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28[Mips Assembler] Add support for OR macro with imediate opperandJack Carter
Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Add support of RDSEED defined in AVX2 extensionMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Enhance boolean simplification to handle 16-/64-bit RDRANDMichael Liao
- RDRAND always clears the destination value when a random value is not available (i.e. CF == 0). This value is truncated or zero-extended as the false boolean value to be returned. Boolean simplification needs to skip this 'zext' or 'trunc' node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28[Mips Assembler] Add alias definitions for jalJack Carter
Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Make Win32 put the SRet address into EAX, fixes PR15556Timur Iskhodzhanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178291 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Specify CPUs on the PPC bswap-load-store testHal Finkel
Otherwise, the CHECK-NOT's might trigger depending on the host's CPU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178287 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Only enable 64-bit bswap DAG combines for PPC64Hal Finkel
Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were added for bswap with load/store. This is because these combines are really only valid in 64-bit mode, regardless of the CPU (and this was not being checked). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Non optimizable objc_retainBlock calls are not forwarding.Michael Gottesman
Since we handle optimizable objc_retainBlocks through strength reduction in OptimizableIndividualCalls, we know that all code after that point will only see non-optimizable objc_retainBlock calls. IsForwarding is only called by functions after that point, so it is ok to just classify objc_retainBlock as non-forwarding. <rdar://problem/13249661>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28[ObjCARC] Strength reduce objc_retainBlock -> objc_retain if the ↵Michael Gottesman
objc_retainBlock is optimizable. If an objc_retainBlock has the copy_on_escape metadata attached to it AND if the block pointer argument only escapes down the stack, we are allowed to strength reduce the objc_retainBlock to to an objc_retain and thus optimize it. Current there is logic in the ARC data flow analysis to handle this case which is complicated and involved making distinctions in between objc_retainBlock and objc_retain in certain places and considering them the same in others. This patch simplifies said code by: 1. Performing the strength reduction in the initial ARC peephole analysis (ObjCARCOpts::OptimizeIndividualCalls). 2. Changes the ARC dataflow analysis (which runs after the peephole analysis) to consider all objc_retainBlock calls to not be optimizable (since if the call was optimizable, we would have strength reduced it already). This patch leaves in the infrastructure in the ARC dataflow analysis to handle this case, which due to 2 will just be dead code. I am doing this on purpose to separate the removal of the old code from the testing of the new code. <rdar://problem/13249661>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Remove -O3.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Add the PPC64 ldbrx/stdbrx instructionsHal Finkel
These are 64-bit load/store with byte-swap, and available on the P7 and the A2. Like the similar instructions for 16- and 32-bit words, these are matched in the target DAG-combine phase against load/store-bswap pairs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser
the upper bit is set. They should always be zero-extended, not sign extended. Added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Move test since it depends on the X86 backend.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma
Remove noV4T gp-relative instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28AArch64: implement GICv3 system registersTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Add the PPC64 popcntd instructionHal Finkel
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and tell TTI about it so that popcount-loop recognition will know about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28[tsan] make sure memset/memcpy/memmove are not inlined in tsan modeKostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Revert "Updated ELF relocation test for .eh_frame section"Michael Gottesman
This reverts commit c8d65364223a04b179958a50a4bf0f89b21dd7d2. This broke a bunch of the buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructionsHal Finkel
There were a few places where kill flags were not being set correctly, and where 32-bit instruction variants were being used with 64-bit registers. After r178180, this code was being triggered causing llc to assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Revert "Adding DIImportedModules to DIScopes."David Blaikie
This reverts commit 342d92c7a0adeabc9ab00f3f0d88d739fe7da4c7. Turns out we're going with a different schema design to represent DW_TAG_imported_modules so we won't need this extra field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Check if Type is a vector before calling function Type::getVectorNumElements.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178208 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27This patch follows is a follow up to r178171, which uses the register Preston Gurd
form of call in preference to memory indirect on Atom. In this case, the patch applies the optimization to the code for reloading spilled registers. The patch also includes changes to sibcall.ll and movgs.ll, which were failing on the Atom buildbot after the first patch was applied. This patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Updated ELF relocation test for .eh_frame sectionJack Carter
Made sure we were looking a correct section Added Mips32/64 as an extra check Updated llvm-objdump to generate symbolic info for Mips relocations git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27[ms-inline asm] Add support of imm displacement before bracketed memoryChad Rosier
expression. Specifically, this syntax: ImmDisp [ BaseReg + Scale*IndexReg + Disp ] We don't currently support: ImmDisp [ Symbol ] rdar://13518671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178186 91177308-0d34-0410-b5e6-96231b3b80d8
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