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2011-01-24fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24merge all the "crash tests" into crash.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24fix PR9017, a bug where we'd assert when promoting in unreachableChris Lattner
code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24fix PR9015, a crash linking recursive metadata.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24enhance SRoA to promote allocas that are used by PHI nodes. This oftenChris Lattner
occurs because instcombine sinks loads and inserts phis. This kicks in on such apps as 175.vpr, eon, 403.gcc, xalancbmk and a bunch of times in spec2006 in some app that uses std::deque. This resolves the last of rdar://7339113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Enhance SRoA to promote allocas that are used by selects in someChris Lattner
common cases. This triggers a surprising number of times in SPEC2K6 because min/max idioms end up doing this. For example, code from the STL ends up looking like this to SRoA: %202 = load i64* %__old_size, align 8, !tbaa !3 %203 = load i64* %__old_size, align 8, !tbaa !3 %204 = load i64* %__n, align 8, !tbaa !3 %205 = icmp ult i64 %203, %204 %storemerge.i = select i1 %205, i64* %__n, i64* %__old_size %206 = load i64* %storemerge.i, align 8, !tbaa !3 We can now promote both the __n and the __old_size allocas. This addresses another chunk of rdar://7339113, poor codegen on stringswitch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Simplify some code with no functionality change. Make the test a lot moreNick Lewycky
robust against smarter optimizations, using the power of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Add support for the --noexecstack option.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Add support for lowercase variants.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Enhance SRoA to be more aggressive about scalarization of aggregate allocasChris Lattner
that have PHI or select uses of their element pointers. This can often happen when instcombine sinks two loads into a successor, inserting a phi or select. With this patch, we can scalarize the alloca, but the pinned elements are not yet promoted. This is still a win for large aggregates where only one element is used. This fixes rdar://8904039 and part of rdar://7339113 (poor codegen on stringswitch). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23remove an old hack that avoided creating MMX datatypes. TheChris Lattner
X86 backend has been fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Use value ranges to fold ext(trunc) in SCEV when possible.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola
Add support for SHT_X86_64_UNWIND. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-22Pass sret arguments through the stack instead of through registers in Sparc ↵Venkatraman Govindaraju
backend. It makes the code generated more compliant with the sparc32 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-22Added ICC, FCC as uses of movcc instruction to generate correct code when ↵Venkatraman Govindaraju
-mattr=v9 is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Actually check memcpy lengths, instead of just commenting aboutDan Gohman
how they should be checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Sparc backend: Venkatraman Govindaraju
Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Just because we have determined that an (fcmp | fcmp) is true for A < B,Owen Anderson
A == B, and A > B, does not mean we can fold it to true. We still need to check for A ? B (A unordered B). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Last round of fixes for movw + movt global address codegen.Evan Cheng
1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",Bruno Cardoso Lopes
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Implement support for byval arguments in Sparc backend.Venkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Revert "Object: Renable the tests now that none of the build bots complain ↵Michael J. Spencer
about aliasing." This reverts commit 281f3901b7b0869929caf8946c1ad1228bc38922. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Enable support for precise scheduling of the instruction selectionAndrew Trick
DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21fix PR9013, an infinite loop in instcombine.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Object: Renable the tests now that none of the build bots complain about ↵Michael J. Spencer
aliasing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Don't try to pull vector bitcasts that change the number of elements throughNick Lewycky
a select. A vector select is pairwise on each element so we'd need a new condition with the right number of elements to select on. Fixes PR8994. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Add a constant folding of casts from zero to zero. Fixes PR9011!Nick Lewycky
While here, I'd like to complain about how vector is not an aggregate type according to llvm::Type::isAggregateType(), but they're listed under aggregate types in the LangRef and zero vectors are stored as ConstantAggregateZero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relativeEvan Cheng
value, the "add pc" must be CSE'ed at the same time. We could follow the same approach as T2 by adding pseudo instructions that combine the ldr + "add pc". But the better approach is to use movw + movt (which I will enable soon), so I'll leave this as a TODO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Implement requiredTransitiveTobias Grosser
The PassManager did not implement the transitivity of requiredTransitive. This was unnoticed since 2006. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add testcases for clz encodingBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Fix the encoding and parsing of clrex instructionBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add cdp/cdp2 instructions for thumb/thumb2Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Disable objdump-trivial-object.test. It is broken on powerpc-darwin9.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20- Use a more appropriate name for Owen's ARM Parser isMCR hack since the ↵Bruno Cardoso Lopes
same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add mcr*2 and mr*c2 support to thumb2 targetsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add mcr* and mr*c support to thumb targetsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Disable this test until I can figure out why it's broken. Not xfailed because itMichael J. Spencer
usese 100% CPU and times out, so it's annoying to run it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20At -O123 the early-cse pass is run before instcombine has run. According to myDuncan Sands
auto-simplier the transform most missed by early-cse is (zext X) != 0 -> X != 0. This patch adds this transform and some related logic to InstructionSimplify and removes some of the logic from instcombine (unfortunately not all because there are several situations in which instcombine can improve things by making new instructions, whereas instsimplify is not allowed to do this). At -O2 this often results in more than 15% more simplifications by early-cse, and results in hundreds of lines of bitcode being eliminated from the testsuite. I did see some small negative effects in the testsuite, for example a few additional instructions in three programs. One program, 483.xalancbmk, got an additional 35 instructions, which seems to be due to a function getting an additional instruction and then being inlined all over the place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123911 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher
to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Sorry, several patches in one.Evan Cheng
TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Object: Add some tests!Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Sparc backend: Implements a delay slot filler that attempt to fill delay slotsVenkatraman Govindaraju
with useful instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20If we can, lower the multiply part of a umulo/smulo call to a libcallEric Christopher
with an invalid type then split the result and perform the overflow check normally. Fixes the 32-bit parts of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Fix debug info for merged global.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-19Similarly, analyze truncate through multiply.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-19Add a missed SCEV fold that is required to continue analyzing the IR producedNick Lewycky
by indvars through the scev expander. trunc(add x, y) --> add(trunc x, y). Currently SCEV largely folds the other way which is probably wrong, but preserved to minimize churn. Instcombine doesn't do this fold either, demonstrating a missed optz'n opportunity on code doing add+trunc+add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-19Fix the encoding of mrrc and mcrr family of instructions. Also add testcases ↵Bruno Cardoso Lopes
for mcr and mrc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
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