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2013-03-27Adding DIImportedModules to DIScopes.David Blaikie
This is just the basic groundwork for supporting DW_TAG_imported_module but I wanted to commit this before pushing support further into Clang or LLVM so that this rather churny change is isolated from the rest of the work. The major churn here is obviously adding another field (within the common DIScope prefix) to all DIScopes (files, classes, namespaces, lexical scopes, etc). This should be the last big churny change needed for DW_TAG_imported_module/using directive support/PR14606. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178099 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel
As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've added some asserts to make sure that we're not). As it turns out, we're not currently handling the Darwin case correctly (I've added a FIXME in the test case). I've tried adding various implied register definitions/uses to force the spill without success, so I'll need to address this later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add XTEST codegen supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen
All Intel CPUs since Yonah look a lot alike, at least at the granularity of the scheduling models. We can add more accurate models for processors that aren't Sandy Bridge if required. Haswell will probably need its own. The Atom processor and anything based on NetBurst is completely different. So are the non-Intel chips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Use multiple virtual registers in PPC CR spillingHal Finkel
Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel
simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Fix PRFCHW test on non-x86 buildsMichael Liao
- 'prefetch' intrinsics are only lowered when SSE is available. On non-X86 builds, 'generic' CPU is used and stops lowering any prefetch intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178046 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add PREFETCHW codegen supportMichael Liao
- Add 'PRFCHW' feature defined in AVX2 ISA extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add test case for commit r178031.Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178038 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: mark most intrinsics as readnone v2Christian Konig
They read from constant register space anyway. v2: fix lit tests Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Patch by Gordon Keiser!Joe Abbey
If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add asan/msan to the list of available features in LIT test runnerAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177994 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Fix SCEV forgetMemoizedResults should search and destroy backedge exprs.Andrew Trick
Fixes PR15570: SEGV: SCEV back-edge info invalid after dead code removal. Indvars creates a SCEV expression for the loop's back edge taken count, then determines that the comparison is always true and removes it. When loop-unroll asks for the expression, it contains a NULL SCEVUnknkown (as a CallbackVH). forgetMemoizedResults should invalidate the loop back edges expression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Remove testcase. It's failing on some platforms but not others.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Hmm...not failing...oddBill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Temporarily XFAIL this test until Michael can look at it.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26[ObjCARC Annotations] Added support for displaying the state of pointers at ↵Michael Gottesman
the bottom/top of BBs of the ARC dataflow analysis for both bottomup and topdown analyses. This will allow for verification and analysis of the merge function of the data flow analyses in the ARC optimizer. The actual implementation of this feature is by introducing calls to the functions llvm.arc.annotation.{bottomup,topdown}.{bbstart,bbend} which are only declared. Each such call takes in a pointer to a global with the same name as the pointer whose provenance is being tracked and a pointer whose name is one of our Sequence states and points to a string that contains the same name. To ensure that the optimizer does not consider these annotations in any way, I made it so that the annotations are considered to be of IC_None type. A test case is included for this commit and the previous ObjCARCAnnotation commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177952 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Revise alignment checking/calculation on 256-bit unaligned memory accessMichael Liao
- It's still considered aligned when the specified alignment is larger than the natural alignment; - The new alignment for the high 128-bit vector should be min(16, alignment) as the pointer is advanced by 16, a power-of-2 offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177947 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)Michael Liao
- Handle the case where the result of 'insert_subvect' is bitcasted before 'extract_subvec'. This removes the redundant insertf128/extractf128 pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177945 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Add an -mcpu option to a test that is apparently scheduler-sensitive.Jakob Stoklund Olesen
This should fix the clang-atom-d2700-ubuntu-rel buildbot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177943 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable some unsafe-fp-math DAG-combine transformation after legalization.Shuxin Yang
For instance, following transformation will be disabled: x + x + x => 3.0f * x; The problem of these transformations is that it introduces a FP constant, which following Instruction-Selection pass cannot handle. Reviewed by Nadav, thanks a lot! rdar://13445387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Add an optimizer-side test case for ARC bug <rdar://13195034>, fixedJohn McCall
in the frontend with @clang.arc.use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable profiling tests for Hexagon since it doesn't support JIT.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177917 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25llvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32.NAKAMURA Takumi
I know it is incorrect and they'd fail with +Asserts for win32 targets, though. I'll try to fix them tonight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25XFAIL some of the generic CodeGen tests for Hexagon.Jyotsna Verma
test/CodeGen/Generic/2008-02-20-MatchingMem.ll: Test contains inline assembly not supported by Hexagon. Following tests are XFAILed due to multiple return values which Hexagon doesn't support. test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll test/CodeGen/Generic/select-cc.ll test/CodeGen/Generic/vector.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177912 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Fix a bug in fast-math fadd/fsub simplification. Shuxin Yang
The problem is that the code mistakenly took for granted that following constructor is able to create an APFloat from a *SIGNED* integer: APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value) rdar://13486998 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177906 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25XFAIL DebugInfo tests for Hexagon.Jyotsna Verma
Hexagon does not support -filetype=obj(direct object generation) flag. Therefore, the following tests are being XFAILed: test/DebugInfo/dwarf-public-names.ll test/DebugInfo/member-pointers.ll test/DebugInfo/two-cus-from-same-file.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable Execution Engine tests not supported by Hexagon.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177896 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable, for now, llvm/test/Transforms/GCOVProfiling on win32. I'll ↵NAKAMURA Takumi
investigate them later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177894 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25x86 -- add the XTEST instructionDave Zarzycki
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki
This fixes Apple bug: 13493622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Remove unnecessary attributes from test case.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25[tools][llvm-readobj] print the name of the section when iterating the ↵Shankar Easwaran
symbol table / dynamic symbol table git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Add a GC plugin for ErlangYiannis Tsiouris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Address issues found by Duncan during post-commit review of r177856.Arnaud A. de Grandmaison
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)Arnaud A. de Grandmaison
This simplification happens at 2 places : - using the nsw attribute when the shl / mul is used by a sign test - when the shl / mul is compared for (in)equality to zero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24[NVPTX] Fix handling of vector argumentsJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow TableGen DAG arguments to be just a name.Jakob Stoklund Olesen
DAG arguments can optionally be named: (dag node, node:$name) With this change, the node is also optional: (dag node, node:$name, $name) The missing node is treated as an UnsetInit, so the above is equivalent to: (dag node, node:$name, ?:$name) This syntax is useful in output patterns where we currently require the types of variables to be repeated: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>; This is preferable: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Move X86-dependent test into the right subdirectory.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson
@llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.Manman Ren
Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries between pointers do not include TBAA tags. Add testing case for "placement new". TBAA currently says NoAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Kill every call to @clang.arc.use in the ARC contract phase.John McCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Update test. There may be multiple catches, but those will be cleaned up.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22reorder the fields in DILexicalBlockFile to match the common prefix for DIScopesDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Reverted r176374. In some cases the lit.site.cfg file does not get generated ↵Galina Kistanova
in tools/clang/tools/extra. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma
word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Refactor out the DIFile parameter to DILexicalBlock to refer to the raw ↵David Blaikie
file/directory pair git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22tsan: fix the testDmitry Vyukov
Add missed file from r177717 commit that adds __tsan_vptr_read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177719 91177308-0d34-0410-b5e6-96231b3b80d8
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