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2011-11-01Merging r143194:Bill Wendling
------------------------------------------------------------------------ r143194 | chapuni | 2011-10-28 07:12:22 -0700 (Fri, 28 Oct 2011) | 7 lines Dwarf: [PR11022] Fix emitting DW_AT_const_value(>i64), to be host-endian-neutral. Don't assume APInt::getRawData() would hold target-aware endianness nor host-compliant endianness. rawdata[0] holds most lower i64, even on big endian host. FIXME: Add a testcase for big endian target. FIXME: Ditto on CompileUnit::addConstantFPValue() ? ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@143449 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-01Fixed in r143195. Still it is not "TARGETS" neutral.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@143448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-01Merging r143437:Bill Wendling
------------------------------------------------------------------------ r143437 | efriedma | 2011-10-31 21:49:29 -0700 (Mon, 31 Oct 2011) | 3 lines Make sure we use the right insertion point when instcombine replaces a PHI with another instruction. (Specifically, don't insert an arbitrary instruction before a PHI.) Fixes PR11275. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@143438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-29Merging r143247:Bill Wendling
------------------------------------------------------------------------ r143247 | chapuni | 2011-10-28 16:11:03 -0700 (Fri, 28 Oct 2011) | 1 line test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@143272 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24Merging r142869:Bill Wendling
------------------------------------------------------------------------ r142869 | void | 2011-10-24 16:05:43 -0700 (Mon, 24 Oct 2011) | 4 lines Check the visibility of the global variable before placing it into the stubs table. A hidden variable could potentially end up in both lists. <rdar://problem/10336715> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24Merging r142806:Bill Wendling
------------------------------------------------------------------------ r142806 | grosbach | 2011-10-24 10:26:26 -0700 (Mon, 24 Oct 2011) | 1 line Update test for r142801. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19Merging r142550:Bill Wendling
------------------------------------------------------------------------ r142550 | evancheng | 2011-10-19 15:22:54 -0700 (Wed, 19 Oct 2011) | 1 line Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19Merging r142493:Bill Wendling
------------------------------------------------------------------------ r142493 | chandlerc | 2011-10-19 03:32:19 -0700 (Wed, 19 Oct 2011) | 5 lines Generalize the reading of probability metadata to work for both branches and switches, with arbitrary numbers of successors. Still optimized for the common case of 2 successors for a conditional branch. Add a test case for switch metadata showing up in the BlockFrequencyInfo pass. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19Merging r142492:Bill Wendling
------------------------------------------------------------------------ r142492 | chandlerc | 2011-10-19 03:30:30 -0700 (Wed, 19 Oct 2011) | 7 lines Teach the BranchProbabilityInfo analysis pass to read any metadata encoding of probabilities. In the absense of metadata, it continues to fall back on static heuristics. This allows __builtin_expect, after lowering through llvm.expect a branch instruction's metadata, to actually enter the branch probability model. This is one component of resolving PR2577. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19Merging r142491:Bill Wendling
------------------------------------------------------------------------ r142491 | chandlerc | 2011-10-19 03:12:41 -0700 (Wed, 19 Oct 2011) | 9 lines Add pass printing support to BlockFrequencyInfo pass. The implementation layer already had support for printing the results of this analysis, but the wiring was missing. Now that printing the analysis works, actually bring some of this analysis, and the BranchProbabilityInfo analysis that it wraps, under test! I'm planning on fixing some bugs and doing other work here, so having a nice place to add regression tests and a way to observe the results is really useful. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142546 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19Merging r142168:Bill Wendling
------------------------------------------------------------------------ r142168 | chandlerc | 2011-10-16 18:11:57 -0700 (Sun, 16 Oct 2011) | 8 lines Add a routine to swap branch instruction operands, and update any profile metadata at the same time. Use it to preserve metadata attached to a branch when re-writing it in InstCombine. Add metadata to the canonicalize_branch InstCombine test, and check that it is tranformed correctly. Reviewed by Nick Lewycky! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142545 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19Merging r142537:Bill Wendling
------------------------------------------------------------------------ r142537 | rafael | 2011-10-19 11:48:52 -0700 (Wed, 19 Oct 2011) | 1 line Fix parsing of a line with only a # in it. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16------------------------------------------------------------------------Bill Wendling
r142058 | atrick | 2011-10-14 23:19:55 -0700 (Fri, 14 Oct 2011) | 7 lines Fix SCEVExpander assert during LSR: "argument of incompatible type". Just because we're dealing with a GEP doesn't mean we can assert the SCEV has a pointer type. The fix is simply to ignore the SCEV pointer type, which we really didn't need. Fixes PR11138 webkit crash. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add missing correctness check to ARMTargetLowering::ReconstructShuffle. ↵Eli Friedman
Fixes PR11129. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Update test for disabling of code/data marker labels in ELF.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14OCaml bindings: add some missing functions and testcases.Torok Edwin
The C bindings exposed some APIs that weren't covered by the OCaml bindings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14OCaml bindings: fix infinite recursion on string_of_lltypeTorok Edwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Update live-in lists when splitting critical edges.Jakob Stoklund Olesen
Fixes PR10814. Patch by Jan Sjödin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add X86 ANDN instruction. Including instruction selection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper
processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add value numbers when spilling dead defs.Jakob Stoklund Olesen
When spilling around an instruction with a dead def, remember to add a value number for the def. The missing value number wouldn't normally create problems since there would be an incoming live range as well. However, due to another bug we could spill a dead V_SET0 instruction which doesn't read any values. The missing value number caused an empty live range to be created which is dangerous since it doesn't interfere with anything. This fixes part of PR11125. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13ELF: Fix the section that relocations apply to. Add test to verify. Patch by ↵Michael J. Spencer
Danil Malyshev! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13llvm-object: Add inline relocation information to disassembly.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Reapply r141870, SCEV expansion of post-inc.Andrew Trick
Speculatively reapply to see if this test case still crashes on linux. I may have fixed it in my last checkin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Revert r141870. The test case crashes on linux with data corruption. A ↵Andrew Trick
deeper issue was exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13LSR: Reuse the post-inc expansion of expressions.Andrew Trick
This avoids unnecessary expansion of expressions and allows the SCEV expander to work on expression DAGs, not just trees. Fixes PR11090. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Force CPU type on test so it doesn't accidentally emit movbe instead of ↵Benjamin Kramer
bswap on Intel Atom CPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Mark 'branch indirect' instruction as an indirect branch.Kalle Raiskila
Not having it confused assembly printing of jumptables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13More closely follow libgcc, which has code after the `ret' instruction toBill Wendling
release the stack segment and reset the stack pointer. Place the code in its own MBB to make the verifier happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Revert r141854 because it was causing failures:Bill Wendling
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Should not add instructions to a BB after a return instruction. The machine ↵Bill Wendling
instruction verifier doesn't like this, nor do I. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper
processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Also inflate register classes around inline asm.Jakob Stoklund Olesen
Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12We need to verify that the machine instruction we're using as a replacement forBill Wendling
our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Removed colons from some target datalayout strings in test, since they don't ↵Lang Hames
match the required format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Finish supporting cpp #file/line comments in assembler for error messages. SoKevin Enderby
for cpp pre-processed assembly we give correct filename and line numbers when reporting errors in assembly files when using clang and -integrated-as on .s files. rdar://8998895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12ARM encoding tests for STC.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen
When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Make this test more specific. There are 3 stats that matched "machine-licm".Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher
file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.Jim Grosbach
Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Revert r141529. This is causing failures in the test-suite, like bigstack ↵Bill Wendling
and ReedSolomon. Boo... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Fix PR11106 by correcting a typo that has been in the code for over a year. ThisCameron Zwarich
would have never worked, since the element type of a vector type is never a vector type. Also fix the conditional to be more direct in checking whether EltTy is a vector type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Update test for r141704.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. TakeNick Lewycky
that into account and test for no U's showing up in the middle, which is what we really wanted to test for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Test case for X86 LZCNT instruction selection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141652 91177308-0d34-0410-b5e6-96231b3b80d8
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