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2011-03-30Merging r128577Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-27--- Merging r127800 into '.':Bill Wendling
U test/CodeGen/X86/h-registers-1.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25--- Merging r127239 into '.':Bill Wendling
U test/Makefile U Makefile.rules --- Merging r127240 into '.': U utils/llvm-lit/Makefile --- Merging r127726 into '.': U lib/Support/raw_ostream.cpp --- Merging r127730 into '.': U test/CodeGen/X86/dyn-stackalloc.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25--- Merging r127731 into '.':Bill Wendling
U test/CodeGen/X86/byval2.ll U test/CodeGen/X86/byval4.ll U test/CodeGen/X86/byval.ll U test/CodeGen/X86/byval3.ll U test/CodeGen/X86/byval5.ll --- Merging r127732 into '.': U test/CodeGen/X86/stdarg.ll U test/CodeGen/X86/fold-mul-lohi.ll U test/CodeGen/X86/scalar-min-max-fill-operand.ll U test/CodeGen/X86/tailcallbyval64.ll U test/CodeGen/X86/stride-reuse.ll U test/CodeGen/X86/sse-align-3.ll U test/CodeGen/X86/sse-commute.ll U test/CodeGen/X86/stride-nine-with-base-reg.ll U test/CodeGen/X86/coalescer-commute2.ll U test/CodeGen/X86/sse-align-7.ll U test/CodeGen/X86/sse_reload_fold.ll U test/CodeGen/X86/sse-align-0.ll --- Merging r127733 into '.': U test/CodeGen/X86/peep-vector-extract-concat.ll U test/CodeGen/X86/pmulld.ll U test/CodeGen/X86/widen_load-0.ll U test/CodeGen/X86/v2f32.ll U test/CodeGen/X86/apm.ll U test/CodeGen/X86/h-register-store.ll U test/CodeGen/X86/h-registers-0.ll --- Merging r127734 into '.': U test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll U test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll U test/CodeGen/X86/avoid-lea-scale2.ll U test/CodeGen/X86/lea-3.ll U test/CodeGen/X86/vec_set-8.ll U test/CodeGen/X86/i64-mem-copy.ll U test/CodeGen/X86/x86-64-malloc.ll U test/CodeGen/X86/mmx-copy-gprs.ll U test/CodeGen/X86/vec_shuffle-17.ll U test/CodeGen/X86/2007-07-18-Vector-Extract.ll --- Merging r127775 into '.': U test/CodeGen/X86/constant-pool-remat-0.ll --- Merging r127872 into '.': U utils/lit/lit/TestingConfig.py U lib/Support/raw_ostream.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24--- Merging r127981 into '.':Bill Wendling
U include/llvm/Target/TargetLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86ISelLowering.h U lib/Target/ARM/ARMISelLowering.h U lib/Target/ARM/ARMISelLowering.cpp U lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128194 into '.': G lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128196 into '.': G lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128197 into '.': A test/CodeGen/X86/tailcall-returndup-void.ll G lib/Transforms/Scalar/CodeGenPrepare.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22Fix Win64 va_arg.Bill Wendling
--- Merging r127328 into '.': U test/CodeGen/X86/win64_vararg.ll U lib/Target/X86/X86ISelLowering.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22For PR9500.Bill Wendling
--- Merging r128041 into '.': U test/CodeGen/X86/fast-isel-gep.ll U lib/Target/X86/X86FastISel.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21--- Merging r127780 into '.':Bill Wendling
U test/MC/ELF/tls-i386.s U lib/MC/MCELFStreamer.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14--- Merging r127464 into '.': Bill Wendling
U test/Transforms/InstCombine/select.ll U lib/Transforms/InstCombine/InstCombineSelect.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Merge r127441 from mainline.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Merge r127298 from mainline.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127435 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10For PR9438:Bill Wendling
--- Merging r127350 into '.': D test/CodeGen/X86/2009-03-11-CoalescerBug.ll --- Merging r127351 into '.': A test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll U test/CodeGen/X86/fold-pcmpeqd-2.ll U lib/CodeGen/SimpleRegisterCoalescing.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08--- Reverse-merging r126896 into '.':Bill Wendling
D test/FrontendC/2011-03-02-UnionInitializer.c git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08A few more tests for instruction encodings.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127209 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Turn on list-ilp scheduling by default on x86 and x86-64, fix upEric Christopher
testcases accordingly. Some are currently xfailed and will be filed as bugs to be fixed or understood. Performance results: roughly neutral on SPEC some micro benchmarks in the llvm suite are up between 100 and 150%, only a pair of regressions that are due to be investigated john-the-ripper saw: 10% improvement in traditional DES 8% improvement in BSDI DES 59% improvement in FreeBSD MD5 67% improvement in OpenBSD Blowfish 14% improvement in LM DES Small compile time impact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling
expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Preserve line no. info.Devang Patel
Radar 9097659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Add test for r127138.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Tweak this test. We can analyze what happens and show that we still do theNick Lewycky
right thing, instead of merely being unable to analyze and the transform doesn't occur. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127149 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Add more analysis of the sign bit of an srem instruction. If the LHS is negativeNick Lewycky
then the result could go either way. If it's provably positive then so is the srem. Fixes PR9343 #7! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127146 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-06ConstantInt has some getters which return ConstantInt's or ConstantVector's ofNick Lewycky
the value splatted into every element. Extend this to getTrue and getFalse which by providing new overloads that take Types that are either i1 or <N x i1>. Use it in InstCombine to add vector support to some code, fixing PR8469! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Revert r127073: "Introduce $(ECHOPATH) to print DOSish path string on MSYS ↵Jakob Stoklund Olesen
bash for alternative of $(ECHO)." It broke the llvm-gcc-native-mingw32 buildbot, and we need all of them to be green for the 2.9 branch. Takumi, please reapply after we branch, preferably with a fix ;-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05ptx: add basic intrinsic supportChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Introduce $(ECHOPATH) to print DOSish path string on MSYS bash for ↵NAKAMURA Takumi
alternative of $(ECHO). On mingw and python/w32, lit would not be expected to understand MSYS-style path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Thread comparisons over udiv/sdiv/ashr/lshr exact and lshr nuw/nsw wheneverNick Lewycky
possible. This goes into instcombine and instsimplify because instsimplify doesn't need to check hasOneUse since it returns (almost exclusively) constants. This fixes PR9343 #4 #5 and #8! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Try once again to optimize "icmp (srem X, Y), Y" by turning the comparison intoNick Lewycky
true/false or "icmp slt/sge Y, 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05test/CodeGen/X86/vec_cast.ll: [PR8311] Add explicit -mtriple=x86_64-linux ↵NAKAMURA Takumi
and -mtriple=x86_64-win32. Thanks to Nadav, it might be fixed in r126424. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Improve div/rem node handling on mips. Patch by Akira HatanakaBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Add testcase for r127032Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04When decling to reuse existing expressions that involve casts, ignoreDan Gohman
bitcasts, which are really no-ops here. This fixes slowdowns on MultiSource/Applications/aha and others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Be nice to Xcore and the XMOS assembler and avoid quoting section namesJoerg Sonnenberger
that contain only letters, digits and the characters "_" and ".". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Lowers block address. Currently asserts when relocation model is not PIC. ↵Bruno Cardoso Lopes
Patch by Akira Hatanaka git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04XFAIL for all. These tests are darwin specific anyway.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Revert broken srem logic from r126991.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract ↵Devang Patel
individual variable's info from merged global. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Allow vector shifts (shl,lshr,ashr) on SPU.Kalle Raiskila
There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Allow load from constant on SPU.Kalle Raiskila
A 'load <4 x i32>* null' crashes llc before this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Fold "icmp pred (srem X, Y), Y" like we do for urem. Handle signed comparisonsNick Lewycky
in the urem case, though not the other way around. This is enough to get #3 from PR9343! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126991 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Teach instruction simplify to use constant ranges to solve problems of the formNick Lewycky
"icmp pred %X, CI" and a number of examples where "%X = binop %Y, CI2". Some of these cases (div and rem) used to make it through opt -O2, but the others are probably now making code elsewhere redundant (probably instcombine). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126988 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Followup to r126970: add 64-bit encoding tests for str with reg operand.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04PR9377: Handle x86 str with register operand in a way consistent with gas.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Revert r123908; the code in question is completely untested and wrong.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Bug#9033: For the ELF assembler output, always quote the section name.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Optimize fprintf -> iprintf if there are no floating point argumentsRichard Osborne
and siprintf is available on the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Optimize sprintf -> siprintf if there are no floating point argumentsRichard Osborne
and siprintf is available on the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Optimize printf -> iprintf if there are no floating point argumentsRichard Osborne
and iprintf is available on the target. Currently iprintf is only marked as being available on the XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03PR9352: Always emit a relocation for weak symbols. Not emitting relocationsEli Friedman
for calls to weak symbols with a definition has the appearance of working with LLVM-generated code because weak symbol definitions are put in their own sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126933 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03TableGen should not ignore BX instructions for the ARM disassembler. pr9368.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126931 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Check the ASM, not LLVM IR.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126918 91177308-0d34-0410-b5e6-96231b3b80d8
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