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2009-07-31llvm-mc/X86: Sketch match functions for immediates and memory operands.Daniel Dunbar
Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31PR4662: Fix a crash introduced by the recent LLVMContext changes.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77716 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31switch off of 'Section' onto MCSection. We're not properly usingChris Lattner
MCSection subclasses yet, but this is a step in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .alignEvan Cheng
to ensure the instruction that follows a TBB (when the number of table entries is odd) is 2-byte aligned. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31fix PR4650: we only track sizes for certain objects, so only put somethingChris Lattner
into the mergable section if it is one of our special cases. This could obviously be improved, but this is the minimal fix and restores us to the previous behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77679 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31Add this test back, the check pattern was too strict.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77662 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31Remove this test while I figure out why it is failing.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77659 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31llvm-mc: Match a few X86 instructions.Daniel Dunbar
- This is "experimental" code, I am feeling my way around and working out the best way to do things (and learning tblgen in the process). Comments welcome, but keep in mind this stuff will change radically. - This is enough to match "subb" and friends, but not much else. The next step is to automatically generate the matchers for individual operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng
T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30Do not use abbrev while writing NamedMDNode name.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77637 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30Darwin assembler now recognizes "orn", so remove workaround.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30Darwin assembler now supports "rrx", so remove workaround.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30Cleanup and include code selection for some frame index cases.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30Optimize some common usage patterns of atomic built-ins ↵Evan Cheng
__sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30Add a new register class to describe operands that can't be SP,Dan Gohman
due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29tbb / tbh instructions only branch forward, not backwards.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Add VFP3 D registers to the DPR register class.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Read and write NamedMDNode.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Fix PR4645 which was fallout from the fix for PR4641.Daniel Dunbar
- Call RAUW to delete all instructions (this is a patch from Nick Lewycky). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29xfail for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Change Neon VLDn intrinsics to return multiple values instead of reallyBob Wilson
wide vectors. Likewise, change VSTn intrinsics to take separate arguments for each vector in a multi-vector struct. Adjust tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Just discard the output, no need to turn it back into text.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77439 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29don't dump .bc file to stdout, and simplify this to a trivial testcase.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29fix PR4584 with a trivial patch now that the pieces are in place.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Bulk erasing instructions without RAUWing them is unsafe. Instead, break themNick Lewycky
into a new BB that has no predecessors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77433 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte ↵Evan Cheng
/ halfword. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Add a couple more tests for the ptest intrinsics to make sure we'reEric Christopher
grabbing them all correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77413 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. LowerEric Christopher
to ptest instruction plus setcc. Revamp ptest instruction. Add test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28Slightly reformat LDA tests to ease grepping.Andreas Bolka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77398 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is ↵Evan Cheng
until more optimization goes in). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28Remove support for ORN to workaround <rdar://problem/7096522>.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28Add workaround for <rdar://problem/7098328>.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28fix testcase for previous patch.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77338 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28Fix PR4639, a ELF-TLS regression from some of my refactoring.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28- More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng
- This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28Teach instcombine to respect and preserve inbounds. Add inboundsDan Gohman
to a few tests where it is required for the expected transformation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77290 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is ↵David Goodwin
a dirty word at ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27llvm-mc: Implement .abort fully in the front endDaniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77272 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27Add a new keyword 'inbounds' for use with getelementptr. See theDan Gohman
LangRef.html changes for details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77259 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27Add ".w" suffix for wide thumb-2 instructions.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27Test case to check that separate section is created for a global variable ↵Sanjiv Gupta
specified with section attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77195 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27Change the assembly syntax for nsw, nuw, and exact, putting themDan Gohman
after their associated opcodes rather than before. This makes them a little easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77194 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27update testcase.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77192 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26put normal data into .data instead of .data.rel on elf systems.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77116 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobalChris Lattner
for now. Make the section switching directives more consistent by not including \n and including \t for them all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77107 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bitChris Lattner
and make it more aggressive, we now put: const int G2 __attribute__((weak)) = 42; into the text (readonly) segment like gcc, previously we put it into the data (readwrite) segment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77104 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26Add support for ARM Neon VREV instructions.Bob Wilson
Patch by Anton Korzh, with some modifications from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25add the most expedient hack to fix PR4619, along with a testcase.Chris Lattner
Thanks to Rafael for the great example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77083 91177308-0d34-0410-b5e6-96231b3b80d8
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