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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55680 91177308-0d34-0410-b5e6-96231b3b80d8
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if possible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55673 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55657 91177308-0d34-0410-b5e6-96231b3b80d8
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xfail old test for ppc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55648 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55605 91177308-0d34-0410-b5e6-96231b3b80d8
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8
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combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55579 91177308-0d34-0410-b5e6-96231b3b80d8
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Based on patch by Giorgos Korfiatis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55570 91177308-0d34-0410-b5e6-96231b3b80d8
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the implicit defs onto the remat'ed instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55564 91177308-0d34-0410-b5e6-96231b3b80d8
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shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55556 91177308-0d34-0410-b5e6-96231b3b80d8
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(safely this time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55550 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55540 91177308-0d34-0410-b5e6-96231b3b80d8
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nameless values, such as:
%3 = add i32 4, 2
This fixes the first half of PR2480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55539 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
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when the compare value has a NaN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
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its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.
This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55498 91177308-0d34-0410-b5e6-96231b3b80d8
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Benchmarks/sim/sim, and others on x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55475 91177308-0d34-0410-b5e6-96231b3b80d8
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Re-materialize the src to replace the copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55467 91177308-0d34-0410-b5e6-96231b3b80d8
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Feel free to fix a better way!
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verifier. See PR2711 for details.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8
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the cast operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55374 91177308-0d34-0410-b5e6-96231b3b80d8
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assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55358 91177308-0d34-0410-b5e6-96231b3b80d8
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done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
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and use them to support
bitcast of constants in fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55300 91177308-0d34-0410-b5e6-96231b3b80d8
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/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55295 91177308-0d34-0410-b5e6-96231b3b80d8
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into the call node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55292 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55239 91177308-0d34-0410-b5e6-96231b3b80d8
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integer, PR2318.
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indices that start with an array subscript. x->field[10000] is just
as bad as (*X)[14][10000].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55226 91177308-0d34-0410-b5e6-96231b3b80d8
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These just test that they go through the BE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55208 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55206 91177308-0d34-0410-b5e6-96231b3b80d8
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and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55151 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55145 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55141 91177308-0d34-0410-b5e6-96231b3b80d8
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1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55139 91177308-0d34-0410-b5e6-96231b3b80d8
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has MOV64ri32 and no plain MOV64ri.
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intptr_t type in this case. FastISel can now select simple
getelementptr instructions.
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slowdown in bzip2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55025 91177308-0d34-0410-b5e6-96231b3b80d8
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