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2013-02-16Derive ELF section type from the name in some cases where GNU as doesJoerg Sonnenberger
so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15If bundle alignment is enabled, do not add data to a fragment with instructionsDerek Schuff
With bundle alignment, instructions all get their own MCFragments (unless they are in a bundle-locked group). For instructions with fixups, this is an MCDataFragment. Emitting actual data (e.g. for .long) attempts to re-use MCDataFragments, which we don't want int this case since it leads to fragments which exceed the bundle size. So, don't reuse them in this case. Also adds a test and fixes some formatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14The ARM NEON vector compare instructions take three arguments. However, the Joel Jones
assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14death to extra whitespaceKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14added basic support for Intel ADX instructionsKay Tiong Khoo
-feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175173 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12[ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier
This is complicated by backward labels (e.g., 0b can be both a backward label and a binary zero). The current implementation assumes [0-9]b is always a label and thus it's possible for 0b and 1b to not be interpreted correctly for ms-style inline assembly. However, this is relatively simple to fix in the inline assembly (i.e., drop the [bB]). This patch also limits backward labels to [0-9]b, so that only 0b and 1b are ambiguous. Part of rdar://12470373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174979 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12[ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier
Part of rdar://12470373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11*fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo
*added file for test cases for i386 intel syntax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11AArch64: Undo change to how test was runTim Northover
This broke on Windows, presumably due to interleaving of output streams. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover
This gives a DiagnosticType to all AsmOperands in sight. This replaces all "invalid operand" diagnostics with something more specific. The messages given should still be sufficiently vague that they're not usually actively misleading when LLVM guesses your instruction incorrectly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07[mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka
Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add AArch64 CRC32 instructionsTim Northover
These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add icache prefetch operations to AArch64Tim Northover
This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05[MC] Bundle alignment: Invalidate relaxed fragmentsDerek Schuff
Currently, when a fragment is relaxed, its size is modified, but its offset is not (it gets laid out as a side effect of checking whether it needs relaxation), then all subsequent fragments are invalidated because their offsets need to change. When bundling is enabled, relaxed fragments need to get laid out again, because the increase in size may push it over a bundle boundary. So instead of only invalidating subsequent fragments, also invalidate the fragment that gets relaxed, which causes it to get laid out again. This patch also fixes some trailing whitespace and fixes the bundling-related debug output of MCFragments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05This patch that sets the Mips ELF header flag for Jack Carter
MicroMips architectures. Contributer: Zoran Jovanovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05This patch that sets the EmitAlias flag in td files Jack Carter
and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01Add explicit triples to AArch64 testsTim Northover
Only Linux is supported at the moment, and other platforms quickly fault. As a result these tests would fail on non-Linux hosts. It may be worth making the tests more generic again as more platforms are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31[MC] bundle alignment: prevent padding instructions from crossing bundle ↵Derek Schuff
boundaries git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31Add AArch64 as an experimental target.Tim Northover
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Add a special ARM trap encoding for NaCl.Eli Bendersky
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30This patch implements runtime ARM specificJack Carter
setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30This patch implements runtime Mips specificJack Carter
setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30This patch reworks how llvm targets set Jack Carter
and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29[MC][COFF] Delay handling symbol aliases when writingMichael J. Spencer
Fixes PR14447 and PR9034. Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173839 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper
independent 256-bit lanes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2rus instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 1r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 0r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l4r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,Eli Bendersky
use them in tests that run llvm-dwarfdump. This is in order to make tests as specific as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l5r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25This patch implements parsing the .wordJack Carter
directive for the Mips assembler. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add instruction encodings / disassembly support for l6r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add a warning when there is a macro defintion that has named parameters butKevin Enderby
the body does not use them and it appears the body has positional parameters. This can cause unexpected results as in the added test case. As the darwin version of gas(1) which only supported positional parameters, happened to ignore the named parameters. Now that we want to support both styles of macros we issue a warning in this specific case. rdar://12861644 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Have the integrated assembler give an error if $1 is used as an identifier inKevin Enderby
an expression. Currently this bug causes the line to be ignored in a release build and an assert in a debug build. rdar://13062484 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173195 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add forgotten test case for the x32 commitEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer
rip-rel relocations will be off by one byte. PR15040. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22[MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l3r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
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