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2013-01-04PowerPC: Fix eh_frame relocation for PIC Adhemerval Zanella
This patch fixes the PPC eh_frame definitions for the personality and frame unwinding for PIC objects. It makes PIC build correctly creates relative relocations in the '.rela.eh_frame' segments and thus avoiding a text relocation that generates a DT_TEXTREL segments in link phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02Adds missing aliases for fcom and fcomp instructions without arguments.Kevin Enderby
Patch by Michael M Kuperstein! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21[mips] Fix encoding of BAL instruction. Also, fix assembler test case whichAkira Hatanaka
was not catching the error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Change Lit error redirection to FileCheck to a more common syntax since itEli Bendersky
can potentially cause some bots to fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Add a largish auto-generated test for the aligned bundling feature, along withEli Bendersky
the script generating it. The test should never be modified manually. If anyone needs to change it, please change the script and re-run it. The script is placed into utils/testgen - I couldn't think of a better place, and after some discussion on IRC this looked like a logical location. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Tests for the aligned bundling support added in r170718Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18llvm/test/MC/ELF/comp-dir.s: Appease MSYS Bash.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170410 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add a triple to this test -- it has to be an ELF platform...Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170374 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Prepare LLVM to fix PR14625, exposing a hook in MCContext to manage theChandler Carruth
compilation directory. This defaults to the current working directory, just as it always has, but now an assembler can choose to override it with a custom directory. I've taught llvm-mc about this option and added a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170371 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings / disassembly support for l2r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings for PEEK and ENDIN.Richard Osborne
Previously these were marked with the wrong format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings / disassembly support for rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings for ZEXT and SEXT.Richard Osborne
Previously these were marked with the wrong format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings / disassembly support for 2r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings / disassembly support for 0r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Add tests for disassembly of 1r XCore instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby
immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13Make this Lit config file a bit slimmerEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11revert the test changeHao Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11A newbie try a test commitHao Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Add a test for explicitly exercising the mc-relax-all flag.Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07Add separate statistics for Data and Inst fragments emitted during relaxation.Eli Bendersky
Also fixes a test that was overly-sensitive to the exact order of statistics emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169619 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07Added Mapping Symbols for ARM ELFTim Northover
Before this patch, when you objdump an LLVM-compiled file, objdump tried to decode data-in-code sections as if they were code. This patch adds the missing Mapping Symbols, as defined by "ELF for the ARM Architecture" (ARM IHI 0044D). Patch based on work by Greg Fitzgerald. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169609 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Correct ARM NOP encodingDavid Sehr
The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which causes the emission of a coprocessor instruction rather than "mov r0, r0" as indicated in the comment. The test also checks for the wrong encoding. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Test commit.David Sehr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169410 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Added a option to the disassembler to print immediates as hex.Kevin Enderby
This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169393 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04A test in thid directory was not being run because lit.local.cfg didn'tEli Bendersky
include .ll files. Fix that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169283 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby
which would then cause an assert when printed. rdar://11437956 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Fix initial frame state on powerpc64.Ulrich Weigand
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27The section is .debug_line.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168666 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Make this test less sensitive.Eli Bendersky
It currently assumes register numbering and any harmless change in the X86 register naming makes it fail. It's enough to match the register names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-25Add support for .cfi_register now that it is easy to extent the representationRafael Espindola
to support it. Original patch with the parsing and plumbing by the PaX team and Roman Divacky. I added the bits in MCDwarf.cpp and the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-23Implement .cfi_undefined. Based on a patch from PaX team, updated byRafael Espindola
Roman Divacky. I just added the testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21Mips direct object xgot supportJack Carter
This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14This patch is in preparation for adding medium code model support to theBill Schmidt
PPC64 target. The five tests modified herein test code generation that is sensitive to the code model selected. So I've added -code-model=small to the RUN commands for each. Since small code model is the default, this has no effect for now; but this prepares us for eventually changing the default to medium code model for PPC64. Test changes verified with small and medium code model as default on powerpc64-unknown-linux-gnu. All tests continue to pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove DOS line endings.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167968 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach
When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Emit relocations from .debug_aranges to .debug_info for asm filesAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13[MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Add test case to verify correct relocs being generated forUlrich Weigand
TLS symbols on PowerPC using the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Convert an improper CodeGen test to a MC test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08Add support of RTM from TSX extensionMichael Liao
- Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-05Fix for PR14264 cause by commit r167237 which did not take into account aKevin Enderby
possible buffer change with a .macro directive. rdar://12637628 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-03[mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka
register is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-02[mips] Fix disassembler test cases.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167326 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01Add support for generating dwarf debugging info with assembly filesKevin Enderby
run through the 'C' preprocessor. That is pick up the file name and line numbers from the cpp hash file line comments for the dwarf file and line numbers tables. rdar://9275556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167237 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31MC: Simple example parser for MC assembly markup.Jim Grosbach
Nothing fancy, just a simple demonstration parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167181 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30ARM: Better disassembly for pc-relative LDR.Jim Grosbach
When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby
is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
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