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Author
2013-02-17
[XCore] Add missing u10 / lu10 instructions.
Richard Osborne
2013-02-17
[XCore] Add missing u6 / lu6 instructions.
Richard Osborne
2013-02-16
MCParser: Reject .balign with non-pow2 alignments.
Benjamin Kramer
2013-02-16
Derive ELF section type from the name in some cases where GNU as does
Joerg Sonnenberger
2013-02-15
If bundle alignment is enabled, do not add data to a fragment with instructions
Derek Schuff
2013-02-14
The ARM NEON vector compare instructions take three arguments. However, the
Joel Jones
2013-02-14
death to extra whitespace
Kay Tiong Khoo
2013-02-14
added basic support for Intel ADX instructions
Kay Tiong Khoo
2013-02-14
Revert r15266. This fixes llvm.org/pr15266.
Rafael Espindola
2013-02-14
Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
Kristof Beyls
2013-02-12
[ms-inline asm] Add support for lexing binary integers with a [bB] suffix.
Chad Rosier
2013-02-12
added test cases for r174920 (prefetch disassembly)
Kay Tiong Khoo
2013-02-12
[ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.
Chad Rosier
2013-02-11
*fixed disassembly of some i386 system insts with intel syntax
Kay Tiong Khoo
2013-02-11
AArch64: Undo change to how test was run
Tim Northover
2013-02-11
Make use of DiagnosticType to provide better AArch64 diagnostics.
Tim Northover
2013-02-07
[mips] Add definition of JALR instruction which has two register operands. Ch...
Akira Hatanaka
2013-02-06
Add AArch64 CRC32 instructions
Tim Northover
2013-02-06
Add icache prefetch operations to AArch64
Tim Northover
2013-02-05
[MC] Bundle alignment: Invalidate relaxed fragments
Derek Schuff
2013-02-05
This patch that sets the Mips ELF header flag for
Jack Carter
2013-02-05
This patch that sets the EmitAlias flag in td files
Jack Carter
2013-02-01
Add explicit triples to AArch64 tests
Tim Northover
2013-01-31
[MC] bundle alignment: prevent padding instructions from crossing bundle boun...
Derek Schuff
2013-01-31
Add AArch64 as an experimental target.
Tim Northover
2013-01-30
Add a special ARM trap encoding for NaCl.
Eli Bendersky
2013-01-30
This patch implements runtime ARM specific
Jack Carter
2013-01-30
This patch implements runtime Mips specific
Jack Carter
2013-01-30
This patch reworks how llvm targets set
Jack Carter
2013-01-29
[MC][COFF] Delay handling symbol aliases when writing
Michael J. Spencer
2013-01-29
Merge SSE and AVX shuffle instructions in the comment printer.
Craig Topper
2013-01-28
Fix 256-bit PALIGNR comment decoding to understand that it works on independe...
Craig Topper
2013-01-27
[XCore] Add missing l2rus instructions.
Richard Osborne
2013-01-27
[XCore] Add missing l2r instructions.
Richard Osborne
2013-01-27
[XCore] Add missing 1r instructions.
Richard Osborne
2013-01-27
[XCore] Add missing 0r instructions.
Richard Osborne
2013-01-26
X86: Decode PALIGN operands so I don't have to do it in my head.
Benjamin Kramer
2013-01-25
Add instruction encodings / disassembly support for l4r instructions.
Richard Osborne
2013-01-25
Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,
Eli Bendersky
2013-01-25
Add instruction encodings / disassembly support for l5r instructions.
Richard Osborne
2013-01-25
This patch implements parsing the .word
Jack Carter
2013-01-23
Add instruction encodings / disassembly support for l6r instructions.
Richard Osborne
2013-01-22
Add instruction encodings / disassembly support for u10 / lu10 instructions.
Richard Osborne
2013-01-22
Add a warning when there is a macro defintion that has named parameters but
Kevin Enderby
2013-01-22
Have the integrated assembler give an error if $1 is used as an identifier in
Kevin Enderby
2013-01-22
Add forgotten test case for the x32 commit
Eli Bendersky
2013-01-22
X86: Make sure we account for the FMA4 register immediate value, otherwise ri...
Benjamin Kramer
2013-01-22
[MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.
Daniel Dunbar
2013-01-21
Add instruction encodings / disassembly support for u6 / lu6 instructions.
Richard Osborne
2013-01-21
Add instruction encoding / disassembly support for ru6 / lru6 instructions.
Richard Osborne
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