| Age | Commit message (Expand) | Author |
|---|
| 2012-05-29 | Add intrinsics, code gen, assembler and disassembler support for the SSE4a ex... | Benjamin Kramer |
| 2012-04-11 | Add retw and lretw instructions. Also, fix Intel syntax parsing for all | Charles Davis |
| 2012-04-03 | Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. | Craig Topper |
| 2012-03-21 | Fix generation of the address size override prefix. Add assertions for | Joerg Sonnenberger |
| 2012-03-13 | Change the X86 assembler to not require a segment register on string | Kevin Enderby |
| 2012-03-12 | Added a missing error check for X86 assembly with mismatched base and index | Kevin Enderby |
| 2012-03-09 | Add the missing call to Error when a bad X86 scale expression is parsed. | Kevin Enderby |
| 2012-03-09 | test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets. | NAKAMURA Takumi |
| 2012-03-06 | Fix the operand ordering on aliases for shld and shrd. PR12173, part 2. | Eli Friedman |
| 2012-03-05 | Make aliases for shld and shrd match gas. PR12173. | Eli Friedman |
| 2012-02-23 | Updated the llvm-mc disassembler C API to support for the X86 target. | Kevin Enderby |
| 2012-02-19 | Add vmfunc instruction to X86 assembler and disassembler. | Craig Topper |
| 2012-02-18 | Add X86 assembler and disassembler support for AMD SVM instructions. Original... | Craig Topper |
| 2012-02-16 | Replace all instances of dg.exp file with lit.local.cfg, since all tests are ... | Eli Bendersky |
| 2012-01-30 | Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,... | Devang Patel |
| 2012-01-30 | Intel syntax. Support .intel_syntax directive. | Devang Patel |
| 2012-01-27 | Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] | Devang Patel |
| 2012-01-24 | Intel Syntax: Extend special hand coded logic, to recognize special instructi... | Devang Patel |
| 2012-01-23 | Intel syntax: Robustify parsing of memory operand's displacement experssion. | Devang Patel |
| 2012-01-23 | Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] | Devang Patel |
| 2012-01-23 | Intel syntax: Parse segment registers. | Devang Patel |
| 2012-01-20 | Intel syntax: Robustify register parsing. | Devang Patel |
| 2012-01-20 | Intel syntax: Parse ... PTR [-8] | Devang Patel |
| 2012-01-20 | Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. | Devang Patel |
| 2012-01-19 | Post process 'and', 'sub' instructions and select better encoding, if available. | Devang Patel |
| 2012-01-19 | Intel syntax: There is no need to create unary expr for simple negative displ... | Devang Patel |
| 2012-01-19 | Post process 'xor', 'or' and 'cmp' instructions and select better encoding, i... | Devang Patel |
| 2012-01-18 | Process instructions after match to select alternative encoding which may be ... | Devang Patel |
| 2012-01-17 | Intel syntax: Fix parser match class to check memory operand size. | Devang Patel |
| 2012-01-17 | Intel syntax: Parse "BYTE PTR [RDX + RCX]" | Devang Patel |
| 2012-01-17 | Intel syntax: Do not unncessarily create plus expression for memory operand d... | Devang Patel |
| 2012-01-17 | Intel syntax: Ignore mnemonic aliases. | Devang Patel |
| 2012-01-17 | Intel syntax: Robustify memory operand parsing. | Devang Patel |
| 2012-01-13 | Add new test. | Devang Patel |
| 2012-01-12 | Remove test case, as Chris suggested. | Devang Patel |
| 2012-01-12 | Add test case to check intel syntax parsing. | Devang Patel |
| 2011-12-15 | Make sure we correctly note the existence of an i8 immediate for vblendvps an... | Eli Friedman |
| 2011-12-12 | XOP instructions and encoding tests. | Jan Sjödin |
| 2011-11-30 | Support for encoding all FMA4 instructions and tablegen patterns for all | Jan Sjödin |
| 2011-11-25 | This patch contains support for encoding FMA4 instructions and | Bruno Cardoso Lopes |
| 2011-11-24 | X86: alias cqo to cqto. | Benjamin Kramer |
| 2011-10-31 | Move test to the X86 directory, note the PR number and only run MC once. | Rafael Espindola |
| 2011-10-27 | Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and | Kevin Enderby |
| 2011-10-23 | Add X86 SARX, SHRX, and SHLX instructions. | Craig Topper |
| 2011-10-23 | Add X86 RORX instruction | Craig Topper |
| 2011-10-19 | Rename PEXTR to PEXT. Add intrinsics for BMI instructions. | Craig Topper |
| 2011-10-16 | Add X86 PEXTR and PDEP instructions. | Craig Topper |
| 2011-10-16 | Add X86 BZHI instruction as well as BMI2 feature detection. | Craig Topper |
| 2011-10-16 | Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does... | Chris Lattner |
| 2011-10-16 | Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3... | Craig Topper |
