| Age | Commit message (Expand) | Author |
|---|
| 2013-03-28 | Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when th... | Gordon Keiser |
| 2013-03-26 | Patch by Gordon Keiser! | Joe Abbey |
| 2013-02-22 | Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc... | Kristof Beyls |
| 2013-02-14 | Make ARMAsmParser accept the correct alignment specifier syntax in instructions. | Kristof Beyls |
| 2012-12-05 | Added a option to the disassembler to print immediates as hex. | Kevin Enderby |
| 2012-11-29 | Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst | Kevin Enderby |
| 2012-10-30 | ARM: Better disassembly for pc-relative LDR. | Jim Grosbach |
| 2012-10-29 | Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target | Kevin Enderby |
| 2012-10-22 | Add support for annotated disassembly output for X86 and arm. | Kevin Enderby |
| 2012-09-06 | Diagnose invalid alignments on duplicating VLDn instructions. | Tim Northover |
| 2012-09-06 | Check for invalid alignment values when decoding VLDn/VSTn (single ln) instru... | Tim Northover |
| 2012-09-06 | Use correct part of complex operand to encode VST1 alignment. | Tim Northover |
| 2012-08-13 | ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines. | Jim Grosbach |
| 2012-08-02 | Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ... | Jiangning Liu |
| 2012-08-02 | Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. | Jiangning Liu |
| 2012-08-02 | Fix #13241, a bug around shift immediate operand for ARM instruction ADR. | Jiangning Liu |
| 2012-07-10 | Fix instruction description of VMOV (between two ARM core registers and two s... | Richard Barton |
| 2012-07-02 | Fix the remaining TCL-style quotes found in the testsuite. This is | Chandler Carruth |
| 2012-07-02 | Convert the uses of '|&' to use '2>&1 |' instead, which works on old | Chandler Carruth |
| 2012-07-02 | Convert all tests using TCL-style quoting to use shell-style quoting. | Chandler Carruth |
| 2012-06-06 | Correct decoder for T1 conditional B encoding | Richard Barton |
| 2012-05-11 | Added the missing bit definition for the 4th bit of the STR (post reg) instru... | Silviu Baranga |
| 2012-05-03 | Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits | Kevin Enderby |
| 2012-05-03 | Fixed disassembler for vstm/vldm ARM VFP instructions. | Silviu Baranga |
| 2012-05-02 | Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures. | Richard Barton |
| 2012-04-26 | Specify cpu to unbreak tests. | Evan Cheng |
| 2012-04-24 | Add missing test cases for ARM VLD3 (single 3-element structure to all lanes) | Kevin Enderby |
| 2012-04-24 | Add missing test cases for ARM VLD4 (single 4-element structure to all lanes) | Kevin Enderby |
| 2012-04-18 | Added support for disassembling unpredictable swp/swpb ARM instructions. | Silviu Baranga |
| 2012-04-18 | Fix the bahavior of the disassembler when decoding unpredictable mrs instruct... | Silviu Baranga |
| 2012-04-18 | Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ... | Silviu Baranga |
| 2012-04-18 | Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocess... | Silviu Baranga |
| 2012-04-18 | Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instruct... | Silviu Baranga |
| 2012-04-17 | Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) | Kevin Enderby |
| 2012-04-11 | Fixed a case of ARM disassembly getting an assert on a bad encoding | Kevin Enderby |
| 2012-04-11 | Fix ARM disassembly of VLD instructions with writebacks. And add test a case | Kevin Enderby |
| 2012-04-11 | Fix a number of problems with ARM fused multiply add/subtract instructions. | Evan Cheng |
| 2012-04-05 | Added support for unpredictable ADC/SBC instructions on ARM, and also fixed s... | Silviu Baranga |
| 2012-04-05 | Added support for handling unpredictable arithmetic instructions on ARM. | Silviu Baranga |
| 2012-04-02 | Added fix in TableGen instruction decoder generation. The decoder now breaks ... | Silviu Baranga |
| 2012-03-25 | Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu | Eli Bendersky |
| 2012-03-22 | Added soft fail checks for the disassembler when decoding some corner cases o... | Silviu Baranga |
| 2012-03-22 | Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDR... | Silviu Baranga |
| 2012-03-22 | Added soft fail cases for the disassembler when decoding MUL instructions on ... | Silviu Baranga |
| 2012-03-21 | Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test | Kevin Enderby |
| 2012-03-20 | The ARM instructions that have an unpredictable behavior when the pc register... | Silviu Baranga |
| 2012-03-06 | Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. | Kevin Enderby |
| 2012-03-01 | Change ARMInstPrinter::printPredicateOperand() so it will not abort if it | Kevin Enderby |
| 2012-02-16 | Replace all instances of dg.exp file with lit.local.cfg, since all tests are ... | Eli Bendersky |
| 2012-02-09 | Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE... | James Molloy |
