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2013-02-13[ms-inline-asm] Add support for memory references that have non-immediateChad Rosier
displacements. rdar://12974533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler
if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto
Fixed bug in tablegen conversion when source pseudo instruction has a different number of arguments than the destination instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer
This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Make jumptables work for -staticReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky
since a caller uses preserved registers across the call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher
assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Finish obviously broken thought.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Fix the lit test added in r174972Paul Redmond
Patch by: Kevin Schoedel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174974 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12PR14562 - Truncation of left shift became undefPaul Redmond
DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12[NVPTX] Disable vector registersJustin Holewinski
Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek
- variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11[NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture ↵Justin Holewinski
is not valid in this case, and was causing incorrect optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174896 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler
same so we put in the comment field an indicator when we think we are emitting the 16 bit version. For the direct object emitter, the difference is important as well as for other passes which need an accurate count of program size. There will be other similar putbacks to this for various instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08DAGCombiner: Constant folding around pre-increment loads/storesHal Finkel
Previously, even when a pre-increment load or store was generated, we often needed to keep a copy of the original base register for use with other offsets. If all of these offsets are constants (including the offset which was combined into the addressing mode), then this is clearly unnecessary. This change adjusts these other offsets to use the new incremented address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.Bob Wilson
Aside from the question of whether we report a warning or an error when we can't satisfy a requested stack object alignment, the current implementation of this is not good. We're not providing any source location in the diagnostics and the current warning is not connected to any warning group so you can't control it. We could improve the source location somewhat, but we can do a much better job if this check is implemented in the front-end, so let's do that instead. <rdar://problem/13127907> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174741 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler
allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add support for SET*_DX10 instructionsTom Stellard
These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add tests for unsupported condition codes.Tom Stellard
All of the le and lt variants are unsupported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174608 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Fix assembly name for SETGT_INTTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Make sure we call externals from libraries properly when -static.Reed Kotler
For example, when we are doing mips16 hard float or soft float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174583 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Enable jumps when in -static mode.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06This is a follow-up on r174446, now taking Atom processors intoEli Bendersky
account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Implement external weak (ELF) symbols on AArch64Tim Northover
Weakly defined symbols should evaluate to 0 if they're undefined at link-time. This is impossible to do with the usual address generation patterns, so we should use a literal pool entry to materlialise the address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Remove this test in the meantime, since it won't pass on Atom. Atom uses leaEli Bendersky
to move the stack pointer in prologs/epilogs. I will fix the test and add it back later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Attempt to recover gdb bot after r174445.Manman Ren
Failure: undefined symbol 'Lline_table_start0'. Root-cause: we use a symbol subtraction to calculate at_stmt_list, but the line table entries are not dumped in the assembly. Fix: use zero instead of a symbol subtraction for Compile Unit 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Test for r174446Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Dwarf: support for LTO where a single object file can have multiple line tablesManman Ren
We generate one line table for each compilation unit in the object file. Reviewed by Eric and Kevin. rdar://problem/13067005 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05[mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka
is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Reapply r174343, with a fix for a scary DAG combine bug where it failed to ↵Owen Anderson
differentiate between the alignment of the base point of a load, and the overall alignment of the load. This caused infinite loops in DAG combine with the original application of this patch. ORIGINAL COMMIT LOG: When the target-independent DAGCombiner inferred a higher alignment for a load, it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Add testcase for post-increment store instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174419 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05[SjLj Prepare] When demoting an invoke instructions to the stack, if the normalChad Rosier
edge is critical, then split it so we can insert the store. rdar://13126179 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174418 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Add a test case for PR14750.Jakob Stoklund Olesen
This was fixed by r174402. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174405 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600: Add tests for instruction predicatesTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600: Emit function name in the AsmPrinterTom Stellard
Emitting the function name allows us to check for it in the FileCheck tests so we can make sure FileCheck is checking the output of the correct function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma
for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Revert r174343, "When the target-independent DAGCombiner inferred a higher ↵NAKAMURA Takumi
alignment for a load," It caused hangups in compiling clang/lib/Parse/ParseDecl.cpp and clang/lib/Driver/Tools.cpp in stage2 on some hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174374 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Link .ARM.exidx with corresponding text section.Logan Chien
The sh_link in the ELF section header of .ARM.exidx should be filled with the section index of the corresponding text section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174372 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05This patch that sets the EmitAlias flag in td files Jack Carter
and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05When the target-independent DAGCombiner inferred a higher alignment for a load,Owen Anderson
it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04[Stack Alignment] emit warning instead of a hard errorManman Ren
Per discussion in rdar://13127907, we should emit a hard error only if people write code where the requested alignment is larger than achievable and assumes the low bits are zeros. A warning should be good enough when we are not sure if the source code assumes the low bits are zeros. rdar://13127907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04Disable a couple more vector splat optimizations on PPC.Benjamin Kramer
I didn't see those because the test case used "not grep". FileCheck the test and XFAIL it, preserving the old optimization, so this can be fixed eventually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04X86: Open up some opportunities for constant folding by postponing shift ↵Benjamin Kramer
lowering. Fixes PR15141. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors.Benjamin Kramer
This required disabling a PowerPC optimization that did the following: input: x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16> lowered to: tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8> x = ADD tmp, tmp The add now gets folded immediately and we're back at the BUILD_VECTOR we started from. I don't see a way to fix this currently so I left it disabled for now. Fix some trivially foldable X86 tests too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174325 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-02Remove the (apparently) unnecessary debug info metadata indirection.David Blaikie
The main lists of debug info metadata attached to the compile_unit had an extra layer of metadata nodes they went through for no apparent reason. This patch removes that (& still passes just as much of the GDB 7.5 test suite). If anyone can show evidence as to why these extra metadata nodes are there I'm open to reverting this patch & documenting why they're there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174266 91177308-0d34-0410-b5e6-96231b3b80d8
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