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2013-02-20DAGCombiner: Fold pointless truncate, bitcast, buildvector seriesArnold Schwaighofer
(2xi32) (truncate ((2xi64) bitcast (buildvector i32 a, i32 x, i32 b, i32 y))) can be folded into a (2xi32) (buildvector i32 a, i32 b). Such a DAG would cause uneccessary vdup instructions followed by vmovn instructions. We generate this code on ARM NEON for a setcc olt, 2xf64, 2xf64. For example, in the vectorized version of the code below. double A[N]; double B[N]; void test_double_compare_to_double() { int i; for(i=0;i<N;i++) A[i] = (double)(A[i] < B[i]); } radar://13191881 Fixes bug 15283. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175670 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Additional fixes for bug 15155.Bill Schmidt
This handles the cases where the 6-bit splat element is odd, converting to a three-instruction sequence to add or subtract two splats. With this fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175663 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Fix PR15267Michael Liao
- When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Fix bug 14779 for passing anonymous aggregates [patch by Kai Nacke].Bill Schmidt
The PPC backend doesn't handle these correctly. This patch uses logic similar to that in the X86 and ARM backends to track these arguments properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175635 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.Jyotsna Verma
Add HexagonMCInst class which adds various Hexagon VLIW annotations. In addition, this class also includes some APIs related to the constant extenders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Fix PR15155: lost vadd/vsplat optimization.Bill Schmidt
During lowering of a BUILD_VECTOR, we look for opportunities to use a vector splat. When the splatted value fits in 5 signed bits, a single splat does the job. When it doesn't fit in 5 bits but does fit in 6, and is an even value, we can splat on half the value and add the result to itself. This last optimization hasn't been working recently because of improved constant folding. To circumvent this, create a pseudo VADD_SPLAT that can be expanded during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20I optimized the following patterns:Elena Demikhovsky
sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Fix thumbv5e frame lowering assertion failure.Logan Chien
It is possible that frame pointer is not found in the callee saved info, thus FramePtrSpillFI may be incorrect if we don't check the result of hasFP(MF). Besides, if we enable the stack coloring algorithm, there will be an assertion to ensure the slot is live. But in the test case, %var1 is not live in the prologue of the function, and we will get the assertion failure. Note: There is similar code in ARMFrameLowering.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175616 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Expand pseudos/macros:Reed Kotler
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19[ms-inline asm] Force the use of a base pointer if the MachineFunction includesChad Rosier
MS-style inline assembly. This is a follow-on to r175334. Forcing a FP to be emitted doesn't ensure it will be used. Therefore, force the base pointer as well. We now treat MS inline assembly in the same way we treat functions with dynamic stack realignment and VLAs. This guarantees the BP will be used to reference parameters and locals. rdar://13218191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19ARM: Allocation hints must make sure to be in the alloc order.Jim Grosbach
When creating an allocation hint for a register pair, make sure the hint for the physical register reference is still in the allocation order. rdar://13240556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175541 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19Fix typoEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris.Benjamin Kramer
Due to the execution order of doFinalization functions, the GC information were deleted before AsmPrinter::doFinalization was executed. Thus, the GCMetadataPrinter::finishAssembly was never called. The patch fixes that by moving the code of the GCInfoDeleter::doFinalization to Printer::doFinalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19ARM NEON: Merge a f32 bitcast of a v2i32 extracteltArnold Schwaighofer
A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler
BtnezT8SltiX16, BtnezT8SltiuX16 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18Comment out the rdar number.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18[fast-isel] Remove an invalid assert.Chad Rosier
If the memcpy has an odd length with an alignment of 2, this would incorrectly assert on the last 1 byte copy. rdar://13202135 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18Expand pseudo/macro BteqzT8SltX16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18Expand macro/pseudo BteqzT8CmpX16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler
This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17Force a cpu for test. It failed on atom due to different scheduling decisions.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16Replace "check:" wth "CHECK:".Jakub Staszak
Also fix one test by changing "vpermilps" to "vpshufd". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling
new features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16[ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier
If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Temporary revert of 175320.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Reinitialize the ivars in the subtarget.Bill Wendling
When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15enable SDISel sincos optimization for GNU environmentsPaul Redmond
- add sincos to runtime library if target triple environment is GNU - added canCombineSinCosLibcall() which checks that sincos is in the RTL and if the environment is GNU then unsafe fpmath is enabled (required to preserve errno) - extended sincos-opt lit test Reviewed by: Hal Finkel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175283 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover
This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15AArch64: refactor frame handling to use movz/movk for overlarge offsets.Tim Northover
In the near future litpools will be in a different section, which means that any access to them is at least two instructions. This makes the case for a movz/movk pair (if total offset <= 32-bits) even more compelling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler
not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao
inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune
It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175183 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky
Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Add lit tests for texture sampling instruction selection.Michel Danzer
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Reapply "s/grep/FileCheck/ in some tests"Andrew Trick
This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85. Use a triple this time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert "s/grep/FileCheck/ in some tests"Andrew Trick
This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3. The FileCheck tests are not equivalent: test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input ; CHECK: jmp init ^ <stdin>:1:2: note: scanning from here .section __TEXT,__text,regular,pure_instructions ^ <stdin>:13:2: note: possible intended match here jmp _init ## TAILCALL ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13temporarily revert the patch due to some conflictsWeiming Zhao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13R600: Add support for 128-bit parametersTom Stellard
NOTE: This is a candidate for the Mesa stable branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13s/grep/FileCheck/ in some testsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13s/grep/FileCheck/ in some testsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao
on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[ms-inline asm] Fix up test case for non-Darwin platforms.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma
instead of redefining separate instructions for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
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