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2011-01-03Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack inEvan Cheng
prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if the adjustment is 4 in 32-bit mode. In the epilogue, takes care to pop to a caller-saved register that's not live at the exit (either return or tailcall instruction). rdar://8771137 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-02Try to reuse the value when lowering memset.Benjamin Kramer
This allows us to compile: void test(char *s, int a) { __builtin_memset(s, a, 15); } into 1 mul + 3 stores instead of 3 muls + 3 stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-02Lower the i8 extension in memset to a multiply instead of a potentially long ↵Benjamin Kramer
series of shifts and ors. We could implement a DAGCombine to turn x * 0x0101 back into logic operations on targets that doesn't support the multiply or it is slow (p4) if someone cares enough. Example code: void test(char *s, int a) { __builtin_memset(s, a, 4); } before: _test: ## @test movzbl 8(%esp), %eax movl %eax, %ecx shll $8, %ecx orl %eax, %ecx movl %ecx, %eax shll $16, %eax orl %ecx, %eax movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret after: _test: ## @test movzbl 8(%esp), %eax imull $16843009, %eax, %eax ## imm = 0x1010101 movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-01Fix darwin bots.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122672 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-01Add support for the 'H' modifier.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-01Update the testAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-01ptx: remove reg-reg addressing mode and st.constChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-01ptx: add store instructionChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-30ptx: add state spacesChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122638 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-29test/CodeGen/X86/negative-sin.ll: FileCheck-ize.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-29test/CodeGen/X86/fp-in-intregs.ll: FileCheck-ize.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122618 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.Bob Wilson
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with an unconditional branch, that branch needs to be deleted before appending the expansion of the BCCi64 to the end of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Fixes PR8823: add-with-overflow-128.llAndrew Trick
In the bottom-up selection DAG scheduling, handle two-address instructions that read/write unspillable registers. Treat the entire chain of two-address nodes as a single live range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is ↵Benjamin Kramer
illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22X86: Lower a select directly to a setcc_carry if possible.Benjamin Kramer
int test(unsigned long a, unsigned long b) { return -(a < b); } compiles to _test: ## @test cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7] sbbl %eax, %eax ## encoding: [0x19,0xc0] ret ## encoding: [0xc3] instead of _test: ## @test xorl %ecx, %ecx ## encoding: [0x31,0xc9] cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7] movl $-1, %eax ## encoding: [0xb8,0xff,0xff,0xff,0xff] cmovael %ecx, %eax ## encoding: [0x0f,0x43,0xc1] ret ## encoding: [0xc3] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22ptx: add ld instruction and testChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22Fix a bug in ReduceLoadWidth that wasn't handling extendingChris Lattner
loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122392 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Reapply 122353-122355 with fixes. 122354 was wrong;Dale Johannesen
the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Add some x86 specific dagcombines for conditional increments.Benjamin Kramer
(add Y, (sete X, 0)) -> cmp X, 1; adc 0, Y (add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y (sub (sete X, 0), Y) -> cmp X, 1; sbb 0, Y (sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y for unsigned foo(unsigned a, unsigned b) { if (a == 0) b++; return b; } we now get: foo: cmpl $1, %edi movl %esi, %eax adcl $0, %eax ret instead of: foo: testl %edi, %edi sete %al movzbl %al, %eax addl %esi, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Revert 122353-122355 for the moment, they broke stuff.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Add a new transform to DAGCombiner.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Get the type of a shift from the shift, not from its shiftDale Johannesen
count operand. These should be the same but apparently are not always, and this is cleaner anyway. This improves the code in an existing test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.Bob Wilson
Type legalization splits up i64 values into pairs of i32 values, which leads to poor quality code when inserting or extracting i64 vector elements. If the vector element is loaded or stored, it can be treated as an f64 value and loaded or stored directly from a VPR register. Use the pre-legalization DAG combiner to cast those vector elements to f64 types so that the type legalizer won't mess them up. Radar 8755338. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122319 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20Cosmetic changes.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20temporarily disable this: PR8823.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results,Chris Lattner
the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is a step towards finishing off PR5443. In the testcase in that bug we now get: movq %rdi, %rax addq %rsi, %rax sbbq %rcx, %rcx testb $1, %cl setne %dl ret instead of: movq %rdi, %rax addq %rsi, %rax movl $0, %ecx adcq $0, %rcx testq %rcx, %rcx setne %dl ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20We lower setb to sbb with the hope that the and will go away, when it Chris Lattner
doesn't, match it back to setb. On a 64-bit version of the testcase before we'd get: movq %rdi, %rax addq %rsi, %rax sbbb %dl, %dl andb $1, %dl ret now we get: movq %rdi, %rax addq %rsi, %rax setb %dl ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20Add comment for testcase for 122206Mon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122210 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19Prevents PerformShuffleCombine from creating a node with an illegal type ↵Mon P Wang
after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19improve the setcc -> setcc_carry optimization to happen moreChris Lattner
consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19now that generic vector types aren't selected onto MMX registers, theseChris Lattner
tests don't need -disable-mmx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19add a general coverage test for overflow intrinsics.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19fix PR8642: if a critical edge has a PHI value that can trap,Chris Lattner
isel is *required* to split the edge. PHI values get evaluated on the edge, not in their predecessor block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19move this test into the ARM test so that it is only run when the arm backendChris Lattner
is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18Restore the behavior of frame lowering before my refactoring.Anton Korobeynikov
It turns out that ppc backend has really weird interdependencies over different hooks and all stuff is fragile wrt small changes. This should fix PR8749 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18Just rename the functions, relying on matching a instruction that has the ↵Benjamin Kramer
same name as a symbol is way too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18Test more than just label names and make test work on non-x86 hosts.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18Fix result type of Neon floating-point comparisons against zero.Bob Wilson
The result vector elements are always integers. Radar 8782191. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17During local stack slot allocation, the materializeFrameBaseRegister functionBill Wendling
may be called. If the entry block is empty, the insertion point iterator will be the "end()" value. Calling ->getParent() on it (among others) causes problems. Modify materializeFrameBaseRegister to take the machine basic block and insert the frame base register at the beginning of that block. (It's very similar to what the code does all ready. The only difference is that it will always insert at the beginning of the entry block instead of after a previous materialization of the frame base register. I doubt that that matters here.) <rdar://problem/8782198> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Fix a DAGCombiner crash when folding binary vector operations with constantBob Wilson
BUILD_VECTOR operands where the element type is not legal. I had previously changed this code to insert TRUNCATE operations, but that was just wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Combine several vector-related DAGCombiner tests.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122101 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Add support for matching psign & plendvb to the x86 targetNate Begeman
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Add a transform to DAG Combiner. This improves theDale Johannesen
code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Don't feed 19 bit immediates to ILA.Kalle Raiskila
Patch (slightly modified) by Visa Putkinen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122052 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson
Radar 8776599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-161. ARM/MC/ELF: A few more ELF relocs for .oJason W Kim
2. Fixed EmitLocalCommonSymbol for ELF (Yes, they exist. :) Test added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach
Canonicalize on tLDRpci and remove tLDRcp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15Don't handle -arm-long-calls in fast isel for now.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15Teach machine cse to commute instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15Add Neon VCVT instructions for f32 <-> f16 conversions.Bob Wilson
Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
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