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2013-03-20Fix PR15296Michael Liao
- Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Refactor the DIFile (2nd) parameter to DITypes to be an MDNode reference to ↵David Blaikie
a raw directory/file pair This makes DIType's first non-tag parameter the same as DIFile's, allowing them to both share the common implementation of getFilename/getDirectory in DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski
A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Move the DIFile operand to DITypes from the 4th operand to the 2nd.David Blaikie
This is another step along the way to making all DIScopes have a common prefix which can be added to in a general manner to support using directives (DW_TAG_imported_module). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177462 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll testHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177434 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Rewrite pre-increment store patterns to use standard memory operands.Ulrich Weigand
Currently, pre-increment store patterns are written to use two separate operands to represent address base and displacement: stwu $rS, $ptroff($ptrreg) This causes problems when implementing the assembler parser, so this commit changes the patterns to use standard (complex) memory operands like in all other memory access instruction patterns: stwu $rS, $dst To still match those instructions against the appropriate pre_store SelectionDAG nodes, the patch uses the new feature that allows a Pat to match multiple DAG operands against a single (complex) instruction operand. Approved by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Prepare to make r0 an allocatable register on PPCHal Finkel
Currently the PPC r0 register is unconditionally reserved. There are two reasons for this: 1. r0 is treated specially (as the constant 0) by certain instructions, and so cannot be used with those instructions as a regular register. 2. r0 is used as a temporary register in the CR-register spilling process (where, under some circumstances, we require two GPRs). This change addresses the first reason by introducing a restricted register class (without r0) for use by those instructions that treat r0 specially. These register classes have a new pseudo-register, ZERO, which represents the r0-as-0 use. This has the side benefit of making the existing target code simpler (and easier to understand), and will make it clear to the register allocator that uses of r0 as 0 don't conflict will real uses of the r0 register. Once the CR spilling code is improved, we'll be able to allocate r0. Adding these extra register classes, for some reason unclear to me, causes requests to the target to copy 32-bit registers to 64-bit registers. The resulting code seems correct (and causes no test-suite failures), and the new test case covers this new kind of asymmetric copy. As r0 is still reserved, no functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.Nadav Rotem
Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Cleanup PPC64 unaligned i64 load/storeHal Finkel
Remove an accidentally-added instruction definition and add a comment in the test case. This is in response to a post-commit review by Bill Schmidt. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Improve long vector sext/zext lowering on ARMRenato Golin
The ARM backend currently has poor codegen for long sext/zext operations, such as v8i8 -> v8i32. This patch addresses this by performing a custom expansion in ARMISelLowering. It also adds/changes the cost of such lowering in ARMTTI. This partially addresses PR14867. Patch by Pete Couperus git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177380 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Don't reserve R31 on PPC64 unless the frame pointer is neededHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177379 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Fix a sign-extension bug in PPCCTRLoopsHal Finkel
Don't sign extend the immediate value from the OR instruction in an LIS/OR pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Fix PPC unaligned 64-bit loads and storesHal Finkel
PPC64 supports unaligned loads and stores of 64-bit values, but in order to use the r+i forms, the offset must be a multiple of 4. Unfortunately, this cannot always be determined by examining the immediate itself because it might be available only via a TOC entry. In order to get around this issue, we additionally predicate the selection of the r+i form on the alignment of the load or store (forcing it to be at least 4 in order to select the r+i form). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Extend global merge pass to optionally consider global constant variables.Quentin Colombet
Also add some checks to not merge globals used within landing pad instructions or marked as "used". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Change test cases to handle unaligned references.Bill Schmidt
Hal Finkel recently added code to allow unaligned memory references for PowerPC. Two tests were temporarily modified with -disable-ppc-unaligned to keep them from failing. This patch adjusts the expected code generation for the unaligned references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Remove unnecessary leading comment characters in lit-only fileDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Include '.test' suffix in target specific lit configs that need itDavid Blaikie
Apparently my final cleanup to use a relevant suffix for these tests before committing r176831 caused them to stop running since lit wasn't configured to run tests with that suffix in those directories (why don't we just have a global suffix list?). So, add the suffix to the relevant directories & fix the test that has bitrotted over the last week due to my debug info schema changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Fix large count and negative constant count handling in PPCCTRLoopsHal Finkel
This commit fixes an assert that would occur on loops with large constant counts (like looping for ((uint32_t) -1) iterations on PPC64). The existing code did not handle counts that it computed to be negative (asserting instead), but these can be created with valid inputs. This bug was discovered by bugpoint while I was attempting to isolate a completely different problem. Also, in writing test cases for the negative-count problem, I discovered that the ori/lsi handling was broken (there was a typo which caused the logic that was supposed to detect these pairs and extract the iteration count to always fail). This has now also been corrected (and is covered by one of the new test cases). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177295 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Cleanup initial-value constants in PPCCTRLoopsHal Finkel
Because the initial-value constants had not been added to the list of instructions considered for DCE the resulting code had redundant constant-materialization instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17Split out filename & directory from DIFile to start generalizing over DIScopesDavid Blaikie
This is the first step to making all DIScopes have a common metadata prefix (so that things (using directives, for example) that can appear in any scope can be added to that common prefix). DIFile is itself a DIScope so the common prefix of all DIScopes cannot be a DIFile - instead it's the raw filename/directory name pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177239 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17Improve PPC VR (Altivec) register spillingHal Finkel
This change cleans up two issues with Altivec register spilling: 1. The spilling code was inefficient (using two instructions, and add and a load, when just one would do) 2. The code assumed that r0 would always be available (true for now, but this will change) The new code handles VR spilling just like GPR spills but forced into r+r mode. As a result, when any VR spills are present, we must now always allocate the register-scavenger spill slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16Remove FIXMEs in PPC test cases related to unaligned loads/storesHal Finkel
As pointed out by Bill in response to r177160, these two FIXMEs can also be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16Add X86 code emitter support AVX encoded MRMDestReg instructions.Craig Topper
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15ARM cost model: Fix costs for some vector selectsArnold Schwaighofer
I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Adding an A15 specific optimization pass for interactions between S/D/Q ↵Silviu Baranga
registers. The pass handles all the required transformations pre-regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15ARM: Fix an old refacto.Benjamin Kramer
Fixes PR15520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177167 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Enable unaligned memory access on PPC for scalar typesHal Finkel
Unaligned access is supported on PPC for non-vector types, and is generally more efficient than manually expanding the loads and stores. A few of the existing test cases were using expanded unaligned loads and stores to test other features (like load/store with update), and for these test cases, unaligned access remains disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Protect PPC Altivec patterns with a predicateHal Finkel
In preparation for the addition of other SIMD ISA extensions (such as QPX) we need to make sure that all Altivec patterns are properly predicated on having Altivec support. No functionality change intended (one test case needed to be updated b/c it assumed that Altivec intrinsics would be supported without enabling Altivec support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Allocate the RS spill slot for any PPC function with spills and a large ↵Hal Finkel
stack frame For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Add a triple to the test.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Unaligned loads should use the VMOVUPS opcode.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handleChad Rosier
the win64 calling convention. rdar://13423768 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Not all PPC functions with a frame pointer need a RS spill slotHal Finkel
We used to add a spill slot for the register scavenger whenever the function has a frame pointer. This is unnecessarily conservative: We may need the spill slot for dynamic stack allocations, and functions with dynamic stack allocations always have a FP, but we might also have a FP for other reasons (such as the user explicitly disabling frame-pointer elimination), and we don't necessarily need a spill slot for those functions. The structsinregs test needed adjustment because it disables FP elimination. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14ARM cost model: Increase cost of some vector selects we do terrible onArnold Schwaighofer
By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Hexagon: Removed asserts regarding alignment and offset.Jyotsna Verma
We are warning the user about the alignment, so we should not assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14R600: Factorize code handling Const Read Port limitationVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix PR15309Michael Liao
- Fix the typo on type checking git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14test commit: remove blank line.Jiong Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Simplify file/directory name handling in DILexicalBlockDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Remove the unused 4th operand for DIFile debug info metadataDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13ARM cost model: Add test case to make sure we would notice a change in CodeGenArnold Schwaighofer
In r176898 I updated the cost model to reflect the fact that sext/zext/cast on v8i32 <-> v8i8 and v16i32 <-> v16i8 are expensive. This test case is so that we make sure to update the cost model once we fix CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Refactor filename/directory in DICompileUnit into a DIFileDavid Blaikie
This is the next step towards making the metadata for DIScopes have a common prefix rather than having to delegate based on their tag type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176913 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Remove unused "isMain" field from DICompileUnitDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176910 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Update debug info test cases with empty SplitDebugFilename field.David Blaikie
This could be 'null' or the empty string, DIDescriptor::getStringField coalesces the two cases anyway so it's just a matter of legible/efficient representation. The change in behavior of the DICompileUnit::get* functions could be subsumed by the full verification check - but ideally that should just be an assertion if we could front-load the actual debug info metadata failure paths. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176907 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Revert the test moves from 176733. Use "REQUIRES: asserts" instead.Jan Wen Voung
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Don't reserve R2 on Darwin/PPCHal Finkel
Now that only the register-scavenger version of the CR spilling code remains, we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in any case where the System V ABI uses it (R0 is special architecturally, and so is reserved under all common ABIs). A few test cases needed to be updated to reflect the register-allocation changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Upgrading debug info test cases to be (more) compatible with the current ↵David Blaikie
debug info format. These cases were found by further work to remove support for debug info versioning. Common cleanups (other than changing the version info in the tag field) included adding the last parameter to compile_units (recently added for fission support) and other cases of trailing fields in lexical blocks, compile units, and subprograms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Remove duplicate test contents.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176831 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Fix a crasher newly introduced in r176659/r176649, where fast-isel tries toNick Lewycky
lower an expect intrinsic that is a constant expression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176830 91177308-0d34-0410-b5e6-96231b3b80d8
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