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2011-12-06PTX: Continue to fix up the register mess.Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other ↵Craig Topper
integer vector loads are promoted to those. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do ↵Craig Topper
both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06[arm-fast-isel] Doublewords only require word-alignment.Chad Rosier
rdar://10528060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Align ARM constant pool islands via their basic block.Jakob Stoklund Olesen
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment is set on the basic block. This is in preparation of supporting ARM constant pool islands with different alignments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05Add definitions of 64-bit extract and insert instrucions and makeAkira Hatanaka
PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 andAkira Hatanaka
O32 with relocation-model=pic too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05Add test case - this input used to crash because of duplicate generation of ↵Hal Finkel
SPILL_CRs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05enable PPC register scavenging by default (update tests and remove some FIXMEs)Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05remove wasted space for extra bit copies of CR2 subregsHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05Add support for vectors of pointers.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03Emit the ctors in the proper order on ARM/EABI.Anton Korobeynikov
Maybe some targets should use this as well. Patch by Evgeniy Stepanov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() sinceVenkatraman Govindaraju
AnalyzeBranch doesn't change the successor, just the order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03Check for stack space more intelligently.Sanjoy Das
libgcc sets the stack limit field in TCB to 256 bytes above the actual allocated stack limit. This means if the function's stack frame needs less than 256 bytes, we can just compare the stack pointer with the stack limit. This should result in lesser calls to __morestack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03Fix a bug in the x86-32 code generated for segmented stacks.Sanjoy Das
Currently LLVM pads the call to __morestack with a add and sub of 8 bytes to esp. This isn't correct since __morestack expects the call to be followed directly by a ret. This commit also adjusts the relevant test-case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03[arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier
rdar://10510150 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02Test cases for 64-bit multiplication and division.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145717 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02Fix test cases to use FileCheck.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02[arm-fast-isel] After promoting a function parameter be sure to update theChad Rosier
argument value type. Otherwise, the sign/zero-extend has no effect on arguments passed via the stack (i.e., undefined high-order bits). rdar://10515467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02specify cpu for test to fix failure on some darwin systems with a g4+ cpuHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02Add instruction selection support for horizontal add/sub of 256-bit floating ↵Craig Topper
point vectors. Also add the test case for 256-bit integer vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02adjust the instruction ordering in some PPC tests: changes due to postRA ↵Hal Finkel
haz. rec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01For 64-bit the rest of the general regs are ok for the q constraint. MakeEric Christopher
sure we can emit both the high and low versions of those registers. Fixes rdar://10392864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01Pass AVX vectors which are arguments to varargs functions on the stack. ↵Eli Friedman
<rdar://problem/10463281>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin
remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30Make GlobalMerge honor the preferred alignment on globals without an ↵Eli Friedman
explicitly specified alignment. <rdar://problem/10497732>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30Add test arch to make it pass on non x86 targetsNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30Add a tripple to the testNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30X86: PerformOrCombine introduced a vselect node with a wrong order of ↵Nadav Rotem
operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29FileCheckize.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145452 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka
tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it ↵Evan Cheng
was generating poor code for some SSE builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps / vxorps so they can participate in execution domain swizzling. This also makes the AVX variants redundant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29If fast-isel fails, remove dead instructions generated during the failed Chad Rosier
attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145425 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.Elena Demikhovsky
Added a test. Thanks Bruno for reviewing the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145403 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Fix shuffle decoding for memory forms for (V)SHUFPS/D.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle ↵Craig Topper
decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow ↵Craig Topper
execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Correctly mark VPERM2F128 as being an FP instruction and add execution ↵Craig Topper
domain fixing support to convert it to VPERM2I128 for AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28Revert r145273 and fix in SelectionDAG::InferPtrAlignment() instead.Evan Cheng
Conservatively returns zero when the GV does not specify an alignment nor is it initialized. Previously it returns ABI alignment for type of the GV. However, if the type is a "packed" type, then the under-specified alignments is attached to the load / store instructions. In that case, the alignment of the type cannot be trusted. rdar://10464621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28DAG combine should not increase alignment of loads / stores with alignment lessEvan Cheng
than ABI alignment. These are loads / stores from / to "packed" data structures. Their alignments are intentionally under-specified. rdar://10301431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge ↵Craig Topper
VPERMILPS/VPERMILPD detection since they are pretty similar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27Take two on rotating the block ordering of loops. My previous attemptChandler Carruth
was centered around the premise of laying out a loop in a chain, and then rotating that chain. This is good for preserving contiguous layout, but bad for actually making sane rotations. In order to keep it safe, I had to essentially make it impossible to rotate deeply nested loops. The information needed to correctly reason about a deeply nested loop is actually available -- *before* we layout the loop. We know the inner loops are already fused into chains, etc. We lose information the moment we actually lay out the loop. The solution was the other alternative for this algorithm I discussed with Benjamin and some others: rather than rotating the loop after-the-fact, try to pick a profitable starting block for the loop's layout, and then use our existing layout logic. I was worried about the complexity of this "pick" step, but it turns out such complexity is needed to handle all the important cases I keep teasing out of benchmarks. This is, I'm afraid, a bit of a work-in-progress. It is still misbehaving on some likely important cases I'm investigating in Olden. It also isn't really tested. I'm going to try to craft some interesting nested-loop test cases, but it's likely to be extremely time consuming and I don't want to go there until I'm sure I'm testing the correct behavior. Sadly I can't come up with a way of getting simple, fine grained test cases for this logic. We need complex loop structures to even trigger much of it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27Rework a bit of the implementation of loop block rotation to not rely soChandler Carruth
heavily on AnalyzeBranch. That routine doesn't behave as we want given that rotation occurs mid-way through re-ordering the function. Instead merely check that there are not unanalyzable branching constructs present, and then reason about the CFG via successor lists. This actually simplifies my mental model for all of this as well. The concrete result is that we now will rotate more loop chains. I've added a test case from Olden highlighting the effect. There is still a bit more to do here though in order to regain all of the performance in Olden. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27remove autoupgrade support for old forms of llvm.prefetch and the oldChris Lattner
trampoline forms. Both of these were correct in LLVM 3.0, and we don't need to support LLVM 2.9 and earlier in mainline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27Upgrade syntax of tests using volatile instructions to use 'load volatile' ↵Chris Lattner
instead of 'volatile load', which is archaic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27remove some old autoupgrade logicChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27Introduce a loop block rotation optimization to the new block placementChandler Carruth
pass. This is designed to achieve one of the important optimizations that the old code placement pass did, but more simply. This is a somewhat rough and *very* conservative version of the transform. We could get a lot fancier here if there are profitable cases to do so. In particular, this only looks for a single pattern, it insists that the loop backedge being rotated away is the last backedge in the chain, and it doesn't provide any means of doing better in-loop placement due to the rotation. However, it appears that it will handle the important loops I am finding in the LLVM test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-26Fix APFloat::convert so that it handles narrowing conversions correctly; itEli Friedman
was returning incorrect values in rare cases, and incorrectly marking exact conversions as inexact in some more common cases. Fixes PR11406, and a missed optimization in test/CodeGen/X86/fp-stack-O0.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145141 91177308-0d34-0410-b5e6-96231b3b80d8
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