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2012-08-06MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel
The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires ↵Craig Topper
custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05Update test to check for r161305Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Add readcyclecounter lowering on PPC64.Hal Finkel
On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov
classes, which were missed for no reason. This fixes PR13377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Refactor and check "onlyReadsMemory" before optimizing builtins.Bob Wilson
This patch is mostly just refactoring a bunch of copy-and-pasted code, but it also adds a check that the call instructions are readnone or readonly. That check was already present for sin, cos, sqrt, log2, and exp2 calls, but it was missing for the rest of the builtins being handled in this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161282 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-031. Redo mips16 instructions to avoid multiple opcodes for same instruction.Akira Hatanaka
Change these to patterns. 2. Add another 16 instructions. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Fix memcmp code-gen to honor -fno-builtin.Bob Wilson
I noticed that SelectionDAGBuilder::visitCall was missing a check for memcmp in TargetLibraryInfo, so that it would use custom code for memcmp calls even with -fno-builtin. I also had to add a new -disable-simplify-libcalls option to llc so that I could write a test for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Fall back to selection DAG isel for calls to builtin functions.Bob Wilson
Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03[arm-fast-isel] Add support for shl, lshr, and ashr.Jush Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Set transient stack alignment in constructor of MipsFrameLowering and re-enableAkira Hatanaka
test o32_cc_vararg.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02llvm/test/CodeGen/X86/fold-pcmpeqd-1.ll: Make sure this is testing without +avx.NAKAMURA Takumi
FIXME: Could +avx be checked here too? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161156 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02llvm/test/CodeGen/X86/fold-pcmpeqd-1.ll: Rewrite expressions to pass ↵NAKAMURA Takumi
regardless of PR11031. - Relax to match even if epilogue (pop %ebp) were emitted. - Assume the return value is stored to %xmm0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161155 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Line endings.Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Added FMA functionality to X86 target.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering andAkira Hatanaka
MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Let PEI::calculateFrameObjectOffsets compute the final stack size rather thanAkira Hatanaka
computing it in MipsFrameLowering::emitPrologue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka
The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31When store nodes or memcpy nodes are created to copy the function callAkira Hatanaka
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and integer offset operands rather than frame object operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31[x86 frame lowering] In 32-bit mode, use ESI as the base pointer.Chad Rosier
Previously, we were using EBX, but PIC requires the GOT to be in EBX before function calls via PLT GOT pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka
single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31MachineSink: Sort the successors before trying to find SuccToSinkTo.Manman Ren
One motivating example is to sink an instruction from a basic block which has two successors: one outside the loop, the other inside the loop. We should try to sink the instruction outside the loop. rdar://11980766 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Clear kill flags in removeCopyByCommutingDef().Jakob Stoklund Olesen
We are extending live ranges, so kill flags are not accurate. They aren't needed until they are recomputed after RA anyway. <rdar://problem/11950722> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161023 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Reverse order of the two branches at end of a basic block if it is profitable.Manman Ren
We branch to the successor with higher edge weight first. Convert from je LBB4_8 --> to outer loop jmp LBB4_14 --> to inner loop to jne LBB4_14 jmp LBB4_8 PR12750 rdar: 11393714 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Consider address spaces for hashing and CSEing DAG nodes. Otherwise two ↵Pete Cooper
loads from different x86 segments but the same address would get CSEd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160987 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-29Revert r160920 and r160919 due to dragonegg and clang selfhost failureManman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Trying to fix the bot by specifying a triple in the failing testing cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160920 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28X86 Peephole: fix PR13475 in optimizeCompare.Manman Ren
It is possible that an instruction can use and update EFLAGS. When checking the safety, we should check the usage of EFLAGS first before declaring it is safe to optimize due to the update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-27Teach CodeGenPrep to look past bitcast when it's duplicating return instructionEvan Cheng
into predecessor blocks to enable tail call optimization. rdar://11958338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160894 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-27Add <imp-def> of super-register when lowering SUBREG_TO_REG.Jakob Stoklund Olesen
Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate a batch of uses of sub_ss and sub_sd in the X86 target.Jakob Stoklund Olesen
These idempotent sub-register indices don't do anything --- They simply map XMM registers to themselves. They no longer affect register classes either since the SubRegClasses field has been removed from Target.td. This patch replaces XMM->XMM EXTRACT_SUBREG and INSERT_SUBREG patterns with COPY_TO_REGCLASS patterns which simply become COPY instructions. The number of IMPLICIT_DEF instructions before register allocation is reduced, and that is the cause of the test case changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Fix call setup for PIC.Akira Hatanaka
Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Update testing case for Atom when disabling rematerialization inManman Ren
TwoAddressInstructionPass. The generated code for Atom has a different code sequence. This is realted to commit r160749. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Disable rematerialization in TwoAddressInstructionPass.Manman Ren
It is redundant; RegisterCoalescer will do the remat if it can't eliminate the copy. Collected instruction counts before and after this. A few extra instructions are generated due to spilling but it is normal to see these kinds of changes with almost any small codegen change, according to Jakob. This also fixed rdar://11830760 where xor is expected instead of movi0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25When a return struct pointer is passed in registers, the called has nothingRafael Espindola
to pop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Eliminate the stack slot used to save the global base register.Akira Hatanaka
The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24Add a cpu to the test. Should fix the atom bot.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24Add a triple to the test.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24In order to correctly compileRafael Espindola
struct s { double x1; float x2; }; __attribute__((regparm(3))) struct s f(int a, int b, int c); void g(void) { f(41, 42, 43); } We need to be able to represent passing the address of s to f (sret) in a register (inreg). Turns out that all that is needed is to not mark them as mutually incompatible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24ELF does not imply GNU/Linux. Do not assume GNU conventions just because weDavid Chisnall
are targeting an ELF platform. Only fold gs-relative (and fs-relative) loads if it is actually sensible to do so for the target platform. This fixes PR13438. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka
Hello world will compile and execute with this patch. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Fix a typo (the the => the)Sylvestre Ledru
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Fixed DAGCombine optimizations which generate select_cc for targetsNadav Rotem
that do not support it (X86 does not lower select_cc). PR: 13428 Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160619 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-21Fix Mips long branch pass.Akira Hatanaka
This pass no longer requires that the global pointer value be saved to the stack or register since it uses bal instruction to compute branch distance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-20Avoid folding loads that are unsafe to move.Jakob Stoklund Olesen
LiveRangeEdit::foldAsLoad() can eliminate a register by folding a load into its only use. Only do that when the load is safe to move, and it won't extend any live ranges. This fixes PR13414. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160575 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-20Split loop exiting edges more aggressively.Jakob Stoklund Olesen
PHIElimination splits critical edges when it predicts it can resolve interference and eliminate copies. It doesn't split the edge if the interference wouldn't be resolved anyway because the phi-use register is live in the critical edge anyway. Teach PHIElimination to split loop exiting edges with interference, even if it wouldn't resolve the interference. This removes the necessary copies from the loop, which is still an improvement from injecting the copies into the loop. The test case demonstrates the improvement. Before: LBB0_1: cmpb $0, (%rdx) leaq 1(%rdx), %rdx movl %esi, %eax je LBB0_1 After: LBB0_1: cmpb $0, (%rdx) leaq 1(%rdx), %rdx je LBB0_1 movl %esi, %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Fix remaining lit tests which were failing when run on an AtomPreston Gurd
processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160520 91177308-0d34-0410-b5e6-96231b3b80d8
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