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AgeCommit message (Expand)Author
2012-09-26Generate an error message instead of asserting or segfaulting when we have aBill Wendling
2012-09-26Generate an error message instead of asserting or segfaulting when we have aBill Wendling
2012-09-25Add missing i64 max/min/umax/umin on 32-bit targetMichael Liao
2012-09-25Fix an illegal tailcall opt where the callee returns a double via xmm while c...Evan Cheng
2012-09-24Mark jump tables in code sections with DataRegion directives.Jim Grosbach
2012-09-24Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky
2012-09-23Revise test to avoid using of 'grep'Michael Liao
2012-09-22Enhance test case of atomic16 to verify inst encoding fixed in r164453.Michael Liao
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier
2012-09-21llvm/test/CodeGen/X86/pr5145.ll: Tweak expressions to match for darwin target.NAKAMURA Takumi
2012-09-21Add missing i8 max/min/umax/umin supportMichael Liao
2012-09-21llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, s/@unaligned_i16_stor...NAKAMURA Takumi
2012-09-21Testcase does not need to be this strict.Chad Rosier
2012-09-21Add newline.Chad Rosier
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier
2012-09-21ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach
2012-09-20Ignore PHI-defs for -new-coalescer interference checks.Jakob Stoklund Olesen
2012-09-20Try to make these tests more portable.Evan Cheng
2012-09-20Fix broken check lines.Benjamin Kramer
2012-09-20Specify cpu to get the correct instruction ordering. Remove XFAIL.Roman Divacky
2012-09-20Specify CPu to prevent failure on ATOM due to different code schedulingMichael Liao
2012-09-20Re-work X86 code generation of atomic ops with spin-loopMichael Liao
2012-09-19Resolve conflicts involving dead vector lanes for -new-coalescer.Jakob Stoklund Olesen
2012-09-19Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArithMichael Liao
2012-09-19Really XFAIL test/CodeGen/PowerPC/structsinregs.ll.Jordan Rose
2012-09-19XFAIL test/CodeGen/PowerPC/structsinregs.llBill Schmidt
2012-09-19Small structs for PPC64 SVR4 must be passed right-justified in registers.Bill Schmidt
2012-09-19Move load_to_switch.ll to test/CodeGen/SPARC/Hans Wennborg
2012-09-18MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648Evan Cheng
2012-09-18Add test for r164155 and remove two tests superseded by ppc64-calls.ll.Roman Divacky
2012-09-18Avoid symbol name clash when filling TOC.Roman Divacky
2012-09-18On PPC64 emit the environment pointer. Patch by Adhemerval Zanella.Roman Divacky
2012-09-18Optimize local func calls to not emit nop for TOC restoration.Roman Divacky
2012-09-18More domain conversion; convert VFP VMOVS to NEON instructions in more cases ...James Molloy
2012-09-18Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng
2012-09-17Merge into undefined lanes under -new-coalescer.Jakob Stoklund Olesen
2012-09-17Add some cases to x86 OptimizeCompare to handle DEC and INC, too.Jan Wen Voung
2012-09-17Fix PR13859Michael Liao
2012-09-17Removed the VMLxForwarding feature for the Cortex-A15 target.Silviu Baranga
2012-09-16Fix the testcase to work on all platforms.Nadav Rotem
2012-09-16The PMOVZXWD family of functions had patterns extends narrow vector types to ...Nadav Rotem
2012-09-15X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.Benjamin Kramer
2012-09-15Handled unaligned load/stores properly in Mips16 Akira Hatanaka
2012-09-13Fix both the test for zero and what we do if we have a zero forEric Christopher
2012-09-13Add wider vector/integer support for PR12312Michael Liao
2012-09-13Enhance type legalization on bitcast from vector to integerMichael Liao
2012-09-13Fix test case to avoid PIC magic.Jakob Stoklund Olesen
2012-09-13Fix the TCRETURNmi64 bug differently.Jakob Stoklund Olesen
2012-09-13Revert r163761 "Don't fold indexed loads into TCRETURNmi64."Jakob Stoklund Olesen
2012-09-13This patch introduces A15 as a target in LLVM.Silviu Baranga
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