| Age | Commit message (Expand) | Author |
|---|
| 2013-03-27 | Allocate r0 on PPC | Hal Finkel |
| 2013-03-27 | Remove the link register from the GPR classes on PowerPC. | Bill Schmidt |
| 2013-03-27 | Adding DIImportedModules to DIScopes. | David Blaikie |
| 2013-03-27 | Don't spill PPC VRSAVE on non-Darwin (even in SjLj) | Hal Finkel |
| 2013-03-26 | Add XTEST codegen support | Michael Liao |
| 2013-03-26 | Enable SandyBridgeModel for all modern Intel P6 descendants. | Jakob Stoklund Olesen |
| 2013-03-26 | Use multiple virtual registers in PPC CR spilling | Hal Finkel |
| 2013-03-26 | Update PEI's virtual-register-based scavenging to support multiple simultaneo... | Hal Finkel |
| 2013-03-26 | Fix PRFCHW test on non-x86 builds | Michael Liao |
| 2013-03-26 | Add PREFETCHW codegen support | Michael Liao |
| 2013-03-26 | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. | Jyotsna Verma |
| 2013-03-26 | R600/SI: mark most intrinsics as readnone v2 | Christian Konig |
| 2013-03-25 | Revise alignment checking/calculation on 256-bit unaligned memory access | Michael Liao |
| 2013-03-25 | Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx) | Michael Liao |
| 2013-03-25 | Add an -mcpu option to a test that is apparently scheduler-sensitive. | Jakob Stoklund Olesen |
| 2013-03-25 | Disable some unsafe-fp-math DAG-combine transformation after legalization. | Shuxin Yang |
| 2013-03-25 | llvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32. | NAKAMURA Takumi |
| 2013-03-25 | XFAIL some of the generic CodeGen tests for Hexagon. | Jyotsna Verma |
| 2013-03-25 | Remove unnecessary attributes from test case. | Chad Rosier |
| 2013-03-25 | Add a GC plugin for Erlang | Yiannis Tsiouris |
| 2013-03-24 | [NVPTX] Fix handling of vector arguments | Justin Holewinski |
| 2013-03-23 | Remove the type legality check from the SelectionDAGBuilder when it lowers @l... | Owen Anderson |
| 2013-03-22 | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma |
| 2013-03-22 | Refactor out the DIFile parameter to DILexicalBlock to refer to the raw file/... | David Blaikie |
| 2013-03-22 | R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730 | Michel Danzer |
| 2013-03-22 | Reorder the DIFile field in DILexicalBlock to become a prefix common with oth... | David Blaikie |
| 2013-03-21 | Fix a register-class comparison bug in PPCCTRLoops | Hal Finkel |
| 2013-03-21 | Move the DIFile in DISubprogram to the beginning to be a common prefix along ... | David Blaikie |
| 2013-03-21 | Implement builtin_{setjmp/longjmp} on PPC | Hal Finkel |
| 2013-03-21 | Fix Darwin NEON FP and increase coverage | Renato Golin |
| 2013-03-21 | Remove unused field in DISubprogram | David Blaikie |
| 2013-03-21 | Add support for spilling VRSAVE on PPC | Hal Finkel |
| 2013-03-21 | Correct PPC FRAMEADDR lowering using a pseudo-register | Hal Finkel |
| 2013-03-21 | Avoid NEON SP-FP unless unsafe-math or Darwin | Renato Golin |
| 2013-03-20 | Debug info: refactor the first field of DICompileUnit to be a raw file/direct... | David Blaikie |
| 2013-03-20 | When computing the demanded bits of Load SDNodes, make sure that we are looki... | Nadav Rotem |
| 2013-03-20 | Debug Info: Swap the 2nd and 3rd parameters to DICompileUnit to match the com... | David Blaikie |
| 2013-03-20 | Remove unused field in DICompileUnit | David Blaikie |
| 2013-03-20 | Add a test case for PR15318 fixed in r177472 | Hao Liu |
| 2013-03-20 | Fix PR15296 | Michael Liao |
| 2013-03-20 | Refactor the DIFile (2nd) parameter to DITypes to be an MDNode reference to a... | David Blaikie |
| 2013-03-20 | Propagate DAG node ordering during type legalization and instruction selection | Justin Holewinski |
| 2013-03-19 | Move the DIFile operand to DITypes from the 4th operand to the 2nd. | David Blaikie |
| 2013-03-19 | Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll test | Hal Finkel |
| 2013-03-19 | Rewrite pre-increment store patterns to use standard memory operands. | Ulrich Weigand |
| 2013-03-19 | Prepare to make r0 an allocatable register on PPC | Hal Finkel |
| 2013-03-19 | Optimize sext <4 x i8> and <4 x i16> to <4 x i64>. | Nadav Rotem |
| 2013-03-19 | Cleanup PPC64 unaligned i64 load/store | Hal Finkel |
| 2013-03-19 | Improve long vector sext/zext lowering on ARM | Renato Golin |
| 2013-03-19 | Don't reserve R31 on PPC64 unless the frame pointer is needed | Hal Finkel |
