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2011-03-27--- Merging r127800 into '.':Bill Wendling
U test/CodeGen/X86/h-registers-1.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25--- Merging r127239 into '.':Bill Wendling
U test/Makefile U Makefile.rules --- Merging r127240 into '.': U utils/llvm-lit/Makefile --- Merging r127726 into '.': U lib/Support/raw_ostream.cpp --- Merging r127730 into '.': U test/CodeGen/X86/dyn-stackalloc.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25--- Merging r127731 into '.':Bill Wendling
U test/CodeGen/X86/byval2.ll U test/CodeGen/X86/byval4.ll U test/CodeGen/X86/byval.ll U test/CodeGen/X86/byval3.ll U test/CodeGen/X86/byval5.ll --- Merging r127732 into '.': U test/CodeGen/X86/stdarg.ll U test/CodeGen/X86/fold-mul-lohi.ll U test/CodeGen/X86/scalar-min-max-fill-operand.ll U test/CodeGen/X86/tailcallbyval64.ll U test/CodeGen/X86/stride-reuse.ll U test/CodeGen/X86/sse-align-3.ll U test/CodeGen/X86/sse-commute.ll U test/CodeGen/X86/stride-nine-with-base-reg.ll U test/CodeGen/X86/coalescer-commute2.ll U test/CodeGen/X86/sse-align-7.ll U test/CodeGen/X86/sse_reload_fold.ll U test/CodeGen/X86/sse-align-0.ll --- Merging r127733 into '.': U test/CodeGen/X86/peep-vector-extract-concat.ll U test/CodeGen/X86/pmulld.ll U test/CodeGen/X86/widen_load-0.ll U test/CodeGen/X86/v2f32.ll U test/CodeGen/X86/apm.ll U test/CodeGen/X86/h-register-store.ll U test/CodeGen/X86/h-registers-0.ll --- Merging r127734 into '.': U test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll U test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll U test/CodeGen/X86/avoid-lea-scale2.ll U test/CodeGen/X86/lea-3.ll U test/CodeGen/X86/vec_set-8.ll U test/CodeGen/X86/i64-mem-copy.ll U test/CodeGen/X86/x86-64-malloc.ll U test/CodeGen/X86/mmx-copy-gprs.ll U test/CodeGen/X86/vec_shuffle-17.ll U test/CodeGen/X86/2007-07-18-Vector-Extract.ll --- Merging r127775 into '.': U test/CodeGen/X86/constant-pool-remat-0.ll --- Merging r127872 into '.': U utils/lit/lit/TestingConfig.py U lib/Support/raw_ostream.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24--- Merging r127981 into '.':Bill Wendling
U include/llvm/Target/TargetLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86ISelLowering.h U lib/Target/ARM/ARMISelLowering.h U lib/Target/ARM/ARMISelLowering.cpp U lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128194 into '.': G lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128196 into '.': G lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128197 into '.': A test/CodeGen/X86/tailcall-returndup-void.ll G lib/Transforms/Scalar/CodeGenPrepare.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22Fix Win64 va_arg.Bill Wendling
--- Merging r127328 into '.': U test/CodeGen/X86/win64_vararg.ll U lib/Target/X86/X86ISelLowering.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22For PR9500.Bill Wendling
--- Merging r128041 into '.': U test/CodeGen/X86/fast-isel-gep.ll U lib/Target/X86/X86FastISel.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Merge r127441 from mainline.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Merge r127298 from mainline.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127435 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10For PR9438:Bill Wendling
--- Merging r127350 into '.': D test/CodeGen/X86/2009-03-11-CoalescerBug.ll --- Merging r127351 into '.': A test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll U test/CodeGen/X86/fold-pcmpeqd-2.ll U lib/CodeGen/SimpleRegisterCoalescing.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Turn on list-ilp scheduling by default on x86 and x86-64, fix upEric Christopher
testcases accordingly. Some are currently xfailed and will be filed as bugs to be fixed or understood. Performance results: roughly neutral on SPEC some micro benchmarks in the llvm suite are up between 100 and 150%, only a pair of regressions that are due to be investigated john-the-ripper saw: 10% improvement in traditional DES 8% improvement in BSDI DES 59% improvement in FreeBSD MD5 67% improvement in OpenBSD Blowfish 14% improvement in LM DES Small compile time impact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05ptx: add basic intrinsic supportChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05test/CodeGen/X86/vec_cast.ll: [PR8311] Add explicit -mtriple=x86_64-linux ↵NAKAMURA Takumi
and -mtriple=x86_64-win32. Thanks to Nadav, it might be fixed in r126424. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Improve div/rem node handling on mips. Patch by Akira HatanakaBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Add testcase for r127032Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04When decling to reuse existing expressions that involve casts, ignoreDan Gohman
bitcasts, which are really no-ops here. This fixes slowdowns on MultiSource/Applications/aha and others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Be nice to Xcore and the XMOS assembler and avoid quoting section namesJoerg Sonnenberger
that contain only letters, digits and the characters "_" and ".". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Lowers block address. Currently asserts when relocation model is not PIC. ↵Bruno Cardoso Lopes
Patch by Akira Hatanaka git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04XFAIL for all. These tests are darwin specific anyway.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract ↵Devang Patel
individual variable's info from merged global. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Allow vector shifts (shl,lshr,ashr) on SPU.Kalle Raiskila
There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Allow load from constant on SPU.Kalle Raiskila
A 'load <4 x i32>* null' crashes llc before this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Revert r123908; the code in question is completely untested and wrong.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Bug#9033: For the ELF assembler output, always quote the section name.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Test case for r126864. Radar 9056407.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implementDavid Greene
missing patterns for them. Add a SIMD test subdirectory to hold tests for SIMD instruction selection correctness and quality. ' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Eliminate the unused CodeGenPrepare option to split critical edges.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Extend initial support for primitive types in PTX backendChe-Liang Chiou
- Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Don't re-use existing addrec expansions if they contain casts.Dan Gohman
This fixes PR9259. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Catch more cases where 2-address pass should 3-addressify instructions. ↵Evan Cheng
rdar://9002648. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01Narrow right shifts need to encode their immediates differently from a normalBill Wendling
shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Fix typo introduced by r126661: "Fix a typo which ..."Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Fix a typo which cause dag combine crash. rdar://9059537.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Windows codegen also dies on this, so restrict to the platform it wasDuncan Sands
actually tested on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Make this test x86 specific because the ARM backend can't handle it.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Add preliminary support for .f32 in the PTX backend.Che-Liang Chiou
- Add appropriate TableGen patterns for fadd, fsub, fmul. - Add .f32 as the PTX type for the LLVM float type. - Allow parameters, return values, and global variable declarations to accept the float type. - Add appropriate test cases. Patch by Justin Holewinski git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27Legalize support for fpextend of vector. PR9309.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit ↵NAKAMURA Takumi
"spill/reload frames" for XMMs. It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has ↵Cameron Zwarich
no uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27Give a test file a more sensible name so that it can hold more test cases.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-26Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize ↵Benjamin Kramer
legalized code for large integer arithmetic. 1. Inform users of ADDEs with two 0 operands that it never sets carry 2. Fold other ADDs or ADDCs into the ADDE if possible It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Add patterns to use post-increment addressing for Neon VST1-lane instructions.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24Enable support for vector sext and trunc:Nadav Rotem
Limit the folding of any_ext and sext into the load operation to scalars. Limit the active-bits trunc optimization to scalars. Document vector trunc and vector sext in LangRef. Similar to commit 126080 (for enabling zext). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24Move arch specific tests in arch specific directories.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24Add XCore intrinsic for eeu instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24Merge information about the number of zero, one, and sign bits of live-outCameron Zwarich
registers at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes <rdar://problem/8760114>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memoryEvan Cheng
operands starts at index 2, not 1. rdar://9045024 PR9305 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23Use DW_FORM_data2 for DW_AT_language and let users use ↵Devang Patel
DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23Check only relevant strings in output to increase stability of the tests.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23Add XCore intrinsic for clre instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322 91177308-0d34-0410-b5e6-96231b3b80d8
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