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2009-09-18Fix PR5001 PR5002.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@82191 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16Merge 81821 from mainline.Tanya Lattner
Don't pull a load through a callseq_start if the load's chain has multiple uses, as one of the other uses may be on a path to a different node above the callseq_start, because that leads to a cyclic graph. This problem is exposed when -combiner-global-alias-analysis is used. This fixes PR4880. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81978 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16Merge 81814 from mainline.Tanya Lattner
On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of its result if the condition is false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81977 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-12Fix PR4962.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81650 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-12Merge 80404 from mainline.Tanya Lattner
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81647 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-10Merge 81327 from mainline.Tanya Lattner
Add testcase for r81322 (PR4933). git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81412 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-10Merge 81343 from mainline.Tanya Lattner
When widening a vector load, use the correct chain. This fixes PR4891. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81411 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08Merge 81205 from mainline.Tanya Lattner
Unbreak this test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81271 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08Merge 81204 from mainline (with minor tweak).Tanya Lattner
When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81270 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08Merge 81187 from mainline.Tanya Lattner
fix PR4767, a crash because fp stackifier visited blocks in depth first order, so it wouldn't process unreachable blocks. When compiling at -O0, late dead block elimination isn't done and the bad instructions got to isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81268 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-31Merge from mainline.Tanya Lattner
When undoing a reuse in ReuseInfo::GetRegForReload, check if it was only a sub-register being used. The MachineOperand::getSubReg() method is only valid for virtual registers, so we have to recover the sub-register index manually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@80552 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22Make x86 test actually test x86 code generation. Fix the Eli Friedman
construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22rename test, make more specific.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22Add missing RUN lineAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22Reduce the testAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79703 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22Use CHECK-NEXT to make sure we're only getting one copy of each shuffleBob Wilson
instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79702 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,Bob Wilson
now using shuffles instead of intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79673 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21Add fcopysign instructionsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21Handle 'r' inline asm constraintAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79648 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21Add some tests for vext.16 and vext.32.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-21Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these asBob Wilson
vector shuffles. Temporarily remove the tests for these operations until the new implementation is working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-20Use FileCheck even though this means testing for somethingDale Johannesen
that has nothing to do with the point of the test, per Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79569 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-20Fix an x86 code size regression: prefer RIP-relative addressingDan Gohman
over absolute addressing even in non-PIC mode (unless the address has an index or something else incompatible), because it has a smaller encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79553 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-20Fix an obvious copy-n-paste bug.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-20Use FileCheck for the test run where it's appropriate.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79534 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19Handle 'a' modifier in X86 asms. PR 4742.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79484 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19Make this test platform neutral.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79447 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19Add an x86 peep that narrows TEST instructions to forms that useDan Gohman
a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79439 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19Add support for Neon VEXT (vector extract) shuffles.Bob Wilson
This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19PR4737: Fix a nasty bug in load narrowing with non-power-of-two types.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79415 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18Legalize the shift amount operand of SRL_PARTS, SHL_PARTS, andDan Gohman
SRA_PARTS, as is done for SRL, SHL, and SRA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18Add support for mergeable sections back into the XCore backend.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79368 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18Put data with relocations in the same sections as data without relocations.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79351 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18Make this test less sensitive to assembler differences.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79348 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18force a triple so this passes on darwinChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79345 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18Make tail merging handle blocks with repeated predecessors correctly, andDan Gohman
remove RemoveDuplicateSuccessor, as it is no longer necessary, and because it breaks assumptions made in MachineBasicBlock::isOnlyReachableByFallthrough. Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase for PR4732. test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to it being bugpoint-reduced to the point where it doesn't matter what the condition for the branch is. Add some more interesting code to test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase that originally motivated the RemoveDuplicateSuccessor code, to help verify that the original problem isn't being re-broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79338 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18Fix revsh pattern.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18PowerPC inline asm was emitting two output operandsDale Johannesen
for a single "m" constraint; this is wrong because the opcode of a load or store would have to change in parallel. This patch makes it always compute addresses into a register, which is correct but not as efficient as possible. 7144566. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-17Update getSectionForConstant() to to allow mergable sections to be nulled outRichard Osborne
if not supported by the ELF subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15Fix test on Linux.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79140 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15Reapply r79127. It was fixed by d0k.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15Revert r79127. It was causing compilation errors.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15Change allowsUnalignedMemoryAccesses to take type argument since some targetsEvan Cheng
support unaligned mem access only for certain types. (Should it be size instead?) ARM v7 supports unaligned access for i16 and i32, some v6 variants support it as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15implement support for CHECK-NEXT: in filecheck.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79123 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15Refine EarlyClobber assert in register scavenger.Jakob Stoklund Olesen
It is legal for an inline asm operand to use an earlyclobber register if the use operand is tied to the earlyclobber operand. The issue is discussed here: http://gcc.gnu.org/ml/gcc/1999-04n/msg00431.html We should perhaps let only the machine code verifier worry about these finer details. EarlyClobber operands are not really interesting to the scavenger. This fixes PR4528 for the third time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15specify a target triple so global variable manglings are consistent etc.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79118 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15convert to filecheck.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79117 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15rename this test to sse2.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79116 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15merge a bunch more sse3 tests into sse3.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79115 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15convert test to filecheck format.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79114 91177308-0d34-0410-b5e6-96231b3b80d8
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