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2008-06-04Merge from mainline to fix PR2407.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_23@51962 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-02Merge from mainline.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_23@51869 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-02Merge from mainline.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_23@51868 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22Merge from mainline.Tanya Lattner
Add support for multiple-return values in inline asm. This should get inline asm working as well as it did previously with the CBE with the new MRV support for inline asm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_23@51437 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12Merge from mainline.Tanya Lattner
When transforming a vector_shuffle to a load, the base address must not be an undef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_23@50981 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10Add nounwind.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50931 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10If all sources of a PHI node are defined by an implicit_def, just emit an ↵Evan Cheng
implicit_def instead of a copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50927 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09Add a pattern to do move the low element of a v4f32 and zero extend the rest.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50922 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09Handle a few more cases of folding load i64 into xmm and zero top bits.Evan Cheng
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09Simplify test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50911 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08Use movq to move low half of XMM register and zero-extend the rest.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50874 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08Handle vector move / load which zero the destination register top bits (i.e. ↵Evan Cheng
movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07Add nounwind.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50837 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07Yet another nasty spiller bug.Evan Cheng
%ecx = op store %cl<kill>, (addr) (addr) = op %al It's not safe to unfold the last operand and eliminate store even though %cl is marked kill. It's a sub-register use which means one of its super-register(s) may be used below. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50794 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06Use target triple in tests, not 'realign-stack=0' option. Per request.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50778 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06Fix PR2287. Darwin passes mmx values in register in 64-mode, not Linux.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50716 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05no need for eh infoChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50658 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05Add AsmPrinter support for emitting a directive to declare thatDan Gohman
the code being generated does not require an executable stack. Also, add target-specific code to make use of this on Linux on x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-04Select vector shift with non-immediate i32 shift amount operand by first ↵Evan Cheng
moving the operand into the right register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ↵Evan Cheng
allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02specify an arch for non-x86 hosts.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50576 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01Adding testcase.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50536 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01don't randomly miscompile seto/setuo just because we are in Chris Lattner
ffastmath mode. This fixes rdar://5902801, a miscompilation of gcc.dg/builtins-8.c. Bill, please pull this into Tak. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50523 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30Really commit the test checking the argument lowering behaviour on x86-64 :).Arnold Schwaighofer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50478 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30Tail call optimization improvements:Arnold Schwaighofer
Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29make the vector conversion magic handle multiple results.Chris Lattner
We now compile test2/test3 to: _test2: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End addps %xmm1, %xmm0 ret _test3: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End paddd %xmm1, %xmm0 ret as expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29add support for multiple return values in inline asm. This is a step Chris Lattner
towards PR2094. It now compiles the attached .ll file to: _sad16_sse2: movslq %ecx, %rax ## InlineAsm Start %ecx %rdx %rax %rax %r8d %rdx %rsi ## InlineAsm End ## InlineAsm Start set %eax ## InlineAsm End ret which is pretty decent for a 3 output, 4 input asm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50386 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29Another extract_subreg coalescing bug.Evan Cheng
e.g. vr1024<2> extract_subreg vr1025, 2 If vr1024 do not have the same register class as vr1025, it's not safe to coalesce this away. For example, vr1024 might be a GPR32 while vr1025 might be a GPR64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50385 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Add -march=x86.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Update and_ops.ll according to the recent dagcombiner changes.Dan Gohman
Add a new test, and_ops_more.ll, which is XFAIL'd, to record the parts of and_ops.ll that were affected by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50379 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Test case.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50377 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27Implement a signficant optimization for inline asm:Chris Lattner
When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50315 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Feedback from chrisNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Add a testcase for the recent "handle variable vector insert elt in mem" patchNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50303 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Update tests.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50293 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Special handling for MMX values being passed in either GPR64 or lower ↵Evan Cheng
64-bits of XMM registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50289 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Remove the code from CodeGenPrepare that moved getresult instructionsDan Gohman
to the block that defines their operands. This doesn't work in the case that the operand is an invoke, because invoke is a terminator and must be the last instruction in a block. Replace it with support in SelectionDAGISel for copying struct values into sequences of virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50279 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25MMX argument passing fixes:Evan Cheng
On Darwin / Linux x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2]. On Darwin / Linux x86-32, v1i64 values are passed in memory. On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7]. On Darwin x86-64, v1i64 values are passed in 64-bit GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50257 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Loosen up an assertion to allow intrinsics. I really have noChris Lattner
idea what this code (findNonImmUse) does, so I'm only guessing that this is the right thing. It would be really really nice if this had comments and perhaps switched to SmallPtrSet (hint hint) :) This fixes rdar://5886601, a crash on gcc.target/i386/sse4_1-pblendw.c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50252 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Fix bug in x86 memcpy / memset lowering. If there are trailing bytes not ↵Evan Cheng
handled by rep instructions, a new memcpy / memset is introduced for them. However, since source / destination addresses are already adjusted, their offsets should be zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50239 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-24New test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50229 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23Add support to codegen for getresult instructions with undef operands.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50180 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23Disable stack realignment for these testsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50172 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23Fix test becase ABI stack alignment dropped to 'normal' valueAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50171 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23Fix test, instruction count is valid only if stack is not realignedAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50170 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-21Implement an x86-64 ABI detail of passing structs by hidden firstDan Gohman
argument. The x86-64 ABI requires the incoming value of %rdi to be copied to %rax on exit from a function that is returning a large C struct. Also, add a README-X86-64 entry detailing the missed optimization opportunity and proposing an alternative approach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50075 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-20A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49986 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-20Not all x86-64 machines have sse3 apparently.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49985 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-19rename *.llx -> *.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49970 91177308-0d34-0410-b5e6-96231b3b80d8
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