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2009-08-18Add support for mergeable sections back into the XCore backend.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79368 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18Put data with relocations in the same sections as data without relocations.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79351 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-17Update getSectionForConstant() to to allow mergable sections to be nulled outRichard Osborne
if not supported by the ELF subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15use XCore-specific section with xcore specific cp/dp flags to restore Chris Lattner
support for globals going into the appropriate sections with the flags. This hopefully finishes unbreaking the previous behavior that I broke before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79079 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02Add extra SEXT pattern.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31switch off of 'Section' onto MCSection. We're not properly usingChris Lattner
MCSection subclasses yet, but this is a step in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24Add tests for handling of globals and tls on the XCore. These currently failRichard Osborne
but pass when run against r76652. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76923 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Combine an unaligned store of unaligned load into a memmove.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Expand unaligned 32 bit loads from an address which is a constantRichard Osborne
offset from a 32 bit aligned base as follows: ldw low, base[offset >> 2] ldw high, base[(offset >> 2) + 1] shr low_shifted, low, (offset & 0x3) * 8 shl high_shifted, high, 32 - (offset & 0x3) * 8 or result, low_shifted, high_shifted Expand 32 bit loads / stores with 16 bit alignment into two 16 bit loads / stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Custom lower unaligned 32 bit stores and loads into libcalls. This is Richard Osborne
a big code size win since before they were expanding to upto 16 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15Fix pattern for LD16S_3r, add basic tests to check load / store instructionsRichard Osborne
are being properly selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20Fix for PR4235: to build a floating-point value from integer parts, Eli Friedman
build an integer and cast that to a float. This fixes a crash caused by trying to split an f32 into two f16's. This changes the behavior in test/CodeGen/XCore/fneg.ll because that testcase now triggers a DAGCombine which converts the fneg into an integer operation. If someone is interested, it's probably possible to tweak the test to generate an actual fneg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72162 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18testcase for PR3898Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69473 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15Add the private linkage.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15Don't fold address calculations which use negative offsets intoRichard Osborne
the ADDRspii addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62258 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-14Add pseudo instructions to the XCore for (load|store|load address) of aRichard Osborne
frame index. eliminateFrameIndex will replace these instructions with (LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use. This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame pointer elimination. However since they were marked as implicitly using SP they could not be rematerialised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62238 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03Add support for ISD::TRAP to the XCore backendRichard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18Reapply r59464, this time using the correct typeDuncan Sands
when softening FNEG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59513 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18Revert r59464. It was causing this failure:Bill Wendling
Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/dg.exp ... FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll Failed with signal(SIGABRT) at line 1 while running: llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll | llc -march=xcore > fneg.ll.tmp1.s Assertion failed: (VT.isFloatingPoint() && "Cannot create integer FP constant!"), function getConstantFP, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAG.cpp, line 913. 0 llc 0x0092115c _ZN4llvm3sys18RemoveFileOnSignalERKNS0_4PathEPSs + 844 1 libSystem.B.dylib 0x9217809b _sigtramp + 43 2 ??? 0xffffffff 0x0 + 4294967295 3 libSystem.B.dylib 0x921f0ec2 raise + 26 4 libSystem.B.dylib 0x9220047f abort + 73 5 libSystem.B.dylib 0x921f2063 __assert_rtn + 101 6 llc 0x005a5b0a _ZN4llvm12SelectionDAG13getConmake[1]: *** [check-local] Error 1 make: *** [check] Error 2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-17Add soft float support for a bunch more operations. OriginalDuncan Sands
patch by Richard Osborne, tweaked and extended by your humble servant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59464 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-17Don't produce ADDC/ADDE when expanding SHL unless they are legalRichard Osborne
for the target. This fixes PR3080. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59450 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-14[XCore] Fix expansion of 64 bit add/sub. Don't custom expandRichard Osborne
these operations if ladd/lsub are not available on the current subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-14Add XCore intrinsics for getid (returns thread id) and bitrev (reversesRichard Osborne
bits in a word). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59296 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-07Add basic test for XCore backendRichard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58841 91177308-0d34-0410-b5e6-96231b3b80d8
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