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Age	Commit message (Collapse)	Author
2011-06-30	Pseudo-ize the t2LDMIA_RET instruction.	Jim Grosbach
	It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03	Switch AllocationOrder to using RegisterClassInfo instead of a BitVector	Jakob Stoklund Olesen
	of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26	Be careful about scheduling nodes above previous calls. It increase usages of	Evan Cheng
	more callee-saved registers and introduce copies. Only allows it if scheduling a node above calls would end up lessen register pressure. Call operands also has added ABI restrictions for register allocation, so be extra careful with hoisting them above calls. rdar://9329627 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31	Fix Thumb and Thumb2 tests to be register allocator independent.	Jakob Stoklund Olesen
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02	Now that register allocation properly considers reserved regs, simplify the	Jim Grosbach
	ARM register class allocation order functions to take advantage of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14	Fix test to appease the buildbots.	Bob Wilson
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18	Fix an inverted condition.	Evan Cheng
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16	Make post-ra scheduling, anti-dep breaking, and register scavenger ↵	Evan Cheng
	(conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03	Fix a bug which prevented tail merging of return instructions in	Dan Gohman
	beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16	Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.	Bob Wilson
	This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98635 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15	Branches must be the last instruction in a Thumb2 IT block. Approved by Evan ↵	Sandeep Patel
	Cheng. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8