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2010-08-29Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila
The IDX was treated as byte index, not element index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Fix SPU BE to use all the available return registers.Kalle Raiskila
llc used to assert on the added testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18Fix a bug with insertelement on SPU. Kalle Raiskila
The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila
The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18Change SPU C calling convention to match that described in Kalle Raiskila
"SPU Application Binary Interface Specification, v1.9" by IBM. Specifically: use r3-r74 to pass parameters and the return value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04Make SPU backend handle insertelement and Kalle Raiskila
store for "half vectors" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila
duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110037 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila
such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen
TII::isMoveInstr is going tobe completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26Fix some tests that didn't test anything.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Add the check to the testcase of r106419.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Mark the SPU 'lr' instruction to never have side effects. Kalle Raiskila
This allows the fast regiser allocator to remove redundant register moves. Update a set of tests that depend on the register allocator to be linear scan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithmKalle Raiskila
used to choke llc with the attached test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Fix SPU to cope with vector insertelement to an undef position.Kalle Raiskila
We default to inserting to lane 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Handle loading from/storing to undef pointers on SPU by inserting a Kalle Raiskila
random load/store, rather than crashing llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01Fix handling of 'load' nodes.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Make SPU backend not assert on jump tables.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10Fix encoding of 'sf' and 'sfh' instructions.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04"on the rare occasion the SPU BE produces illegal assembly - it tries to ↵Chris Lattner
emit an add instruction of the form 'a reg, reg, imm'." Patch by Kalle Raiskila! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20teach cellspu how to return i8 and i16 from calls,Chris Lattner
patch by Kalle Raiskila! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09Make sure this test tests something.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09"On SPU, variables in the .bss section that are allocated with the .lcomm ↵Chris Lattner
directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment. this patch disables .lcomm in favour of '.local .comm' Patch by Kalle Raisklia! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Split big test into multiple directories to cater toDale Johannesen
those who don't build all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29From Kalle Raiskila:Chris Lattner
"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions: -in vararg handling, registers are marked to be live, to not confuse the register scavenger -function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-05fix bss section printing for cell, patch by Kalle Raiskila!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97814 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19don't let asm-verbose break the check-next lines in these tests.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-06Teach dag combine to fold the following transformation more aggressively:Evan Cheng
(OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05Delete useless trailing semicolons.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-17Revert this dag combine change:Evan Cheng
Fold (zext (and x, cst)) -> (and (zext x), cst) DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15Fold (zext (and x, cst)) -> (and (zext x), cst).Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng
isl lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22Revert the main portion of r31856. It was causing BranchFoldingDan Gohman
to break up CFG diamonds by banishing one of the blocks to the end of the function, which is bad for code density and branch size. This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the benchmark cited as the reason for the change, however I've examined the code and it looks more like a case of gaming a particular branch than of being generally applicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19Teach lit that the .c files in 'test/CodeGen/CellSPU/useful-harnesses' ↵Daniel Dunbar
aren't tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84460 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11Convert more tests to avoid llvm-as.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09Eliminate more uses of llvm-as and llvm-dis.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-25Updated i128 sext support for CellSPU backend, contributed by Ken Werner (IBM)Scott Michel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80042 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-25Remove obsolete -f flags.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24- Remove SelectSEXTi128 from SPUISelDAGToDAG.cpp, evidently, this is redundantScott Michel
code, according to Anton (I'm not totally convinced, but we can always resurrect patches if we need to do so.) - Start moving CellSPU's tests to prefer FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79958 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24Prefer 'FileCheck' over 'grep'.Scott Michel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79953 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24128-bit sign extension and vector shift cleanups, contributed by Ken WernerScott Michel
(IBM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16Add some generic expansion logic for SMULO and UMULO. Fixes UMULO Eli Friedman
support for x86, and UMULO/SMULO for many architectures, including PPC (PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's not bad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73477 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25Revert 67132. This is breaking some objective-c apps.Evan Cheng
Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67701 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17Don't force promotion of return arguments on the callee.Rafael Espindola
Some architectures (like x86) don't require it. This fixes bug 3779. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67132 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17CellSPU:Scott Michel
Revert inadvertent mis-fix of fneg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67084 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17CellSPU:Scott Michel
- Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-16CellSPU:Scott Michel
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the llvm-gcc bootstrap a bit further along. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8
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