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2011-10-24Merging r142869:Bill Wendling
------------------------------------------------------------------------ r142869 | void | 2011-10-24 16:05:43 -0700 (Mon, 24 Oct 2011) | 4 lines Check the visibility of the global variable before placing it into the stubs table. A hidden variable could potentially end up in both lists. <rdar://problem/10336715> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add missing correctness check to ARMTargetLowering::ReconstructShuffle. ↵Eli Friedman
Fixes PR11129. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen
When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher
file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Test simplification that Ana Pazos noticed.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add testcase for PR11107.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Revert r141569 and r141576.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Reapply r141365 now that PR11107 is fixed.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling
hang, and possibly SPEC/CINT2006/464_h264ref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Reenable tail calls for iOS 5.0 and later.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Reenable use of divmod compiler_rt functions for iOS 5.0 and later.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Peephole optimization for ABS on ARM.Anton Korobeynikov
Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Remove a check from ARM shifted operand isel helper methods, which were blockingCameron Zwarich
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Make this test less sensitive to codegen optimizations.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141195 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30ARM Darwin default relocation model is PIC.Jim Grosbach
This matches clang, so default options in llc and friends are now closer to clang's defaults. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29LSR: rewrite inner loops only.Andrew Trick
Rewriting the entire loop nest now requires -enable-lsr-nested. See PR11035 for some performance data. A few unit tests specifically test nested LSR, and are now under a flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140762 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140761 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28Tighten a ARM dag combine condition to avoid an identity transformation, whichEvan Cheng
ends up introducing a cycle in the DAG. rdar://10196296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26Convert more tests over to the new atomic instructions.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL ↵David Meyer
2011-06-09-TailCallByVal and 2010-11-04-BigByval git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Also match negative offsets for addrmode3 and addrmode5.Jakob Stoklund Olesen
Math is hard, and isScaledConstantInRange() always returned false for negative constants. It was doing unsigned division of negative numbers before casting back to signed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman
worklist, as it may be possible to perform further optimization on them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 ↵Evan Cheng
does not support Thumb2 dsp instructions. rdar://10152911. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20ARM isel bug fix for adds/subs operands.Andrew Trick
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Some additional tests for Thumb atomic load and store (which I somehow ↵Eli Friedman
forgot to commit earlier). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15Some legalization fixes for atomic load and store.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Fix mistake in test runline.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman
same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Directly point debug info to the stack slot of the arugment, instead of ↵Devang Patel
trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs ↵Eli Friedman
failures for atomic laod/store on ARM. (The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Disable these tests harder. They're XFAIL'd, but that means they still run, andNick Lewycky
these tests all infinitely recurse, bringing my system down into swapping hell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Fix fall outs from my recent change on how carry bit is modeled during isel.Evan Cheng
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well. Also fix isel hook to correctly set the optional operand. rdar://10073745 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Atomic pseudos don't use (as in read) CPSR. They clobber it.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Don't fast-isel for atomic load/store; some cases require extra handling ↵Eli Friedman
missing from fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Revert r131152, r129796, r129761. This code is currently consideredDan Gohman
to be unreliable on platforms which require memcpy calls, and it is complicating broader legalize cleanups. It is hoped that these cleanups will make memcpy byval easier to implement in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Don't drop alignment info on local common symbols.Benjamin Kramer
- On COFF the .lcomm directive has an alignment argument. - On ELF we fall back to .local + .comm Based on a patch by NAKAMURA Takumi. Fixes PR9337, PR9483 and PR10128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Permit remat of partial register defs when it is safe.Jakob Stoklund Olesen
An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Prevent remat of partial register redefinitions.Jakob Stoklund Olesen
An instruction that redefines only part of a larger register can never be rematerialized since the virtual register value depends on the old value in other parts of the register. This was fixed for the inline spiller in r138794. This patch fixes the problem for all register allocators, and includes a small test case. <rdar://problem/10032939> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; ↵Eli Friedman
implements 64-bit atomic load/store for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-3164-bit atomic cmpxchg for ARM.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Some minor cleanups for r138845.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng
register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29Add testcase for r138746.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Atomic load/store on ARM/Thumb.Eli Friedman
I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25ARM fix for missing implicit operands on ldmia_ret.Andrew Trick
rdar://10005094: miscompile of 176.gcc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20With the fix in r138164: "Add <imp-def> operands to QQ and QQQQ stack loads."Chad Rosier
-verify-machineinstrs can be enabled for this test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.Chad Rosier
Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
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