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path: root/test/CodeGen/ARM/vector-DAGCombine.ll
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2013-02-12ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach
Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.Bob Wilson
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner
vector type (vectors of size 3). Also included test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14PR9139: Specify ARM/Darwin triple for vector-DAGCombine.ll test.Bob Wilson
The i64_buildvector test in this file relies on the alignment of i64 and f64 types being the same, which is true for Darwin but not AAPCS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125525 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.Bob Wilson
Type legalization splits up i64 values into pairs of i32 values, which leads to poor quality code when inserting or extracting i64 vector elements. If the vector element is loaded or stored, it can be treated as an f64 value and loaded or stored directly from a VPR register. Use the pre-legalization DAG combiner to cast those vector elements to f64 types so that the type legalizer won't mess them up. Radar 8755338. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122319 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Fix a DAGCombiner crash when folding binary vector operations with constantBob Wilson
BUILD_VECTOR operands where the element type is not legal. I had previously changed this code to insert TRUNCATE operations, but that was just wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Combine several vector-related DAGCombiner tests.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122101 91177308-0d34-0410-b5e6-96231b3b80d8