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Age	Commit message (Collapse)	Author
2013-02-22	Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵	Kristof Beyls
	instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18	Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte	Evan Cheng
	aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08	Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵	Craig Topper
	FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21	Add correct set of regression tests for r162094 commit.	Tim Northover
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162276 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21	Add a missing def flag.	Jakob Stoklund Olesen
	* Bad machine code: Explicit definition marked as use * - function: test_cos - basic block: BB#0 L.entry (0x7ff2a2024fd0) - instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def> - operand 0: %D11 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162247 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17	Implement NEON domain switching for scalar <-> S-register vmovs on ARM	Tim Northover
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-26	Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵	Eli Friedman
	location. PR10747, part 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11	Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵	Stepan Dyatkovskiy
	for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10	Revert r146322 to appease buildbots. Original commit message:	Chad Rosier
	Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10	Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵	Stepan Dyatkovskiy
	for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08	Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics	Daniel Dunbar
	sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).", it is failing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08	Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵	Stepan Dyatkovskiy
	for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8