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2013-02-07[mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka
Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: cleanup VGPR encodingTom Stellard
Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Handle VGPR64 destination in copyPhysReg().Tom Stellard
Allows nexuiz to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174655 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Add pattern for mul.Tom Stellard
20 more little piglits with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174654 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: simplify and fix SMRD encodingTom Stellard
The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174653 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: add proper 64bit immediate support v2Tom Stellard
v2: rebased on current upstream Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174652 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add an explicit default processorTom Stellard
This is for the case when no processor is passed to the backend. This prevents the '' is not a recognized processor for this target (ignoring processor) warning from being generated by clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174651 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Identify and simplify idempotent intrinsics. Test case included.Michael Ilseman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174650 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Loop Vectorizer: Refactor Memory Cost ComputationArnold Schwaighofer
We don't want too many classes in a pass and the classes obscure the details. I was going a little overboard with object modeling here. Replace classes by generic code that handles both loads and stores. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174646 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Make sample intrinsic address parameter type overloaded.Tom Stellard
Handle vectors of 1 to 16 integers. Change the intrinsic names to prevent the wrong one from being selected at runtime due to the overloading. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Add basic support for more integer vector types.Tom Stellard
v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07ARM cost model: Add costs for vector selectsArnold Schwaighofer
Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Add pattern for flog2Michel Danzer
22 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174615 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07FDE::dumpHeader(): Forgot to fix one more formatting, ... take two!NAKAMURA Takumi
Excuse me, I could not test it locally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174614 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Consolidate sub register indices.Tom Stellard
Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add support for SET*_DX10 instructionsTom Stellard
These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Fix assembly name for SETGT_INTTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07FDE::dumpHeader(): Forgot to fix one more formatting. It affected bigendian ↵NAKAMURA Takumi
hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174602 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Make sure we call externals from libraries properly when -static.Reed Kotler
For example, when we are doing mips16 hard float or soft float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174583 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07tblgen: Diagnose duplicate includes.Sean Silva
A double inclusion will pretty much always be an error in TableGen, so there's no point going on just to die with "def already defined" or whatnot. I'm not too thrilled about the "public: ... private: ..." to expose the DependenciesMapTy, but I really didn't see a better way to keep that type centralized. It's a smell that indicates that some refactoring is needed to make this code more loosely coupled. This should avoid all bugs of the same nature as PR15189. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Moved some comments due to the recent refactoring of ObjCARC.Michael Gottesman
1. Moved a comment from ObjCARCOpts.cpp -> ObjCARCContract.cpp. 2. Removed a comment from ObjCARCOpts.cpp that was already moved to ObjCARCAliasAnalysis.h/.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174581 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Enable jumps when in -static mode.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07DWARFDebugFrame.cpp: Fix formatting on i686 hosts.NAKAMURA Takumi
FIXME: Are they really truncated to i32 from i64 unconditionally? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174574 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Preserve fast-math flags after reassociation and commutation. Update test casesMichael Ilseman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174571 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Conditionalize constant folding of math intrinsics on the availability of an ↵Owen Anderson
implementation on the host. This is a little bit unfortunate, but until someone decides to implement a full libm for APFloat, we don't have a better way to get this functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Signficantly generalize our ability to constant fold floating point ↵Owen Anderson
intrinsics, including ones on half types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174555 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Code Custodian (trivial whitespace cleanup)Joe Abbey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174550 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Clean up multiple skeleton compile units if we have multiple compileEric Christopher
units coming in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174548 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Remove some dead code.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174547 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06[mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06This is a follow-up on r174446, now taking Atom processors intoEli Bendersky
account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06PPC calling convention cleanup.Bill Schmidt
Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI. Rename things to clarify this. Also delete some code that's been commented out for a long time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06R600: Support for indirect addressing v4Tom Stellard
Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Implement external weak (ELF) symbols on AArch64Tim Northover
Weakly defined symbols should evaluate to 0 if they're undefined at link-time. This is impossible to do with the usual address generation patterns, so we should use a literal pool entry to materlialise the address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add some comments to new frame entriesEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add AArch64 CRC32 instructionsTim Northover
These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add icache prefetch operations to AArch64Tim Northover
This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Initial submission for the attribute group feature.Bill Wendling
Attribute groups are of the form: #0 = attributes { noinline "no-sse" "cpu"="cortex-a8" alignstack=4 } Target-dependent attributes are represented as strings. Attributes can have optional values associated with them. E.g., the "cpu" attribute has the value "cortex-a8". Target-independent attributes are listed as enums inside the attribute classes. Multiple attribute groups can be referenced by the same object. In that case, the attributes are merged together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Remove extra blank line between closing curly brace and 'else'Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174492 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Remove unused private field to suppress a build warning.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174491 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06ARM: Use MCTargetAsmParser::validateTargetOperandClass().Jim Grosbach
Use the validateTargetOperandClass() hook to match literal '#0' operands in InstAlias definitions. Previously this required per-instruction C++ munging of the operand list, but not is handled as a natural part of the matcher. Much better. No additional tests are required, as the pre-existing tests for these instructions exercise the new behaviour as being functionally equivalent to the old. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174488 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Failing builds because a private class member is not being used afterEli Bendersky
initialization is one of the reasons I consider -werror to be shoddy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174485 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add virtual desctructor to FrameEntry to avoid error on delete-non-virtual-dtorEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Tweak check to avoid integer overflow (for insanely large alignments)Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add a 'StringRef' version of hasAttribute.Bill Wendling
Fix the 'operator==' and 'hasAttributes' queries to take into account target-dependent attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174481 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add methods to merge an AttrBuilder into another builder.Bill Wendling
This is useful when parsing an object that references multiple attribute groups. N.B. If both builders have alignments specified, then they should match! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Attempt to recover gdb bot after r174445.Manman Ren
Failure: undefined symbol 'Lline_table_start0'. Root-cause: we use a symbol subtraction to calculate at_stmt_list, but the line table entries are not dumped in the assembly. Fix: use zero instead of a symbol subtraction for Compile Unit 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Fix some formatting & add comments, following Eric's reviewEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174473 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Add the target-dependent (string) attributes from the AttrBuilder to the ↵Bill Wendling
AttributeSet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174467 91177308-0d34-0410-b5e6-96231b3b80d8
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