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2013-02-15Give these callbacks hidden visibility. It is better to not export them moreRafael Espindola
than we need to and some ELF linkers complain about directly accessing symbols with default visibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Don't make assumptions about the mangling of static functions in extern "C"Rafael Espindola
blocks. We still don't have consensus if we should try to change clang or the standard, but llvm should work with compilers that implement the current standard and mangle those functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15[asan] support long double on 64-bit. See ↵Kostya Serebryany
https://code.google.com/p/address-sanitizer/issues/detail?id=151 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Make helpers static. Add missing include so LLVMInitializeObjCARCOpts gets C ↵Benjamin Kramer
linkage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover
This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15AArch64: refactor frame handling to use movz/movk for overlarge offsets.Tim Northover
In the near future litpools will be in a different section, which means that any access to them is at least two instructions. This makes the case for a movz/movk pair (if total offset <= 32-bits) even more compelling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Simplify the 'operator<' for the attribute object.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175252 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15BBVectorize: Cap the number of candidate pairs in each instruction groupHal Finkel
For some basic blocks, it is possible to generate many candidate pairs for relatively few pairable instructions. When many (tens of thousands) of these pairs are generated for a single instruction group, the time taken to generate and rank the different vectorization plans can become quite large. As a result, we now cap the number of candidate pairs within each instruction group. This is done by closing out the group once the threshold is reached (set now at 3000 pairs). Although this will limit the overall compile-time impact, this may not be the best way to achieve this result. It might be better, for example, to prune excessive candidate pairs after the fact the prevent the generation of short, but highly-connected groups. We can experiment with this in the future. This change reduces the overall compile-time slowdown of the csa.ll test case in PR15222 to ~5x. If 5x is still considered too large, a lower limit can be used as the default. This represents a functionality change, but only for very large inputs (thus, there is no regression test). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175251 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Revert "Simplify the attributes '<' comparison function."Anna Zaks
This reverts commit 82c101153fe7b35bce48781fab038e1b8f31a7bd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175250 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler
not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Simplify the attributes '<' comparison function.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Disallow moving load/store instructions past volatile instructions.Akira Hatanaka
Unfortunately, I wasn't able to create a test case that demonstrates the problem I was trying to fix with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Replace usage of SmallSet with BitVector, which is used to keep track ofAkira Hatanaka
defined and used registers. Also add a few helper functions to simplify the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Fix comments and coding style violations. Declare functions to be const.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14The ARM NEON vector compare instructions take three arguments. However, the Joel Jones
assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14The operand listing is very much outdated.Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka
1. Define and use function terminateSearch. 2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator. 3. Delete the line which checks whether an instruction is a pseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14BBVectorize: Remove the remaining instances of std::multimapHal Finkel
All instances of std::multimap have now been replaced by DenseMap<K, std::vector<V> >, and this yields a speedup of 5% on the csa.ll test case from PR15222. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175216 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14BBVectorize: Don't store candidate pairs in a std::multimapHal Finkel
This is another commit on the road to removing std::multimap from BBVectorize. This gives an ~1% speedup on the csa.ll test case in PR15222. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Simplify code. Remove "else after return".Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Update comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175209 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Hexagon: Change insn class to support instruction encoding.Jyotsna Verma
This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14s/bool/LLVMBool/Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Add two new functions to the C API:Bill Wendling
LLVMCreateMemoryBufferWithMemoryRange - exposes MemoryBuffer::getMemBuffer LLVMCreateMemoryBufferWithMemoryRangeCopy - exposes MemoryBuffer::getMemBufferCopy Patch by Moritz Maxeiner! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14added basic support for Intel ADX instructionsKay Tiong Khoo
-feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600/SI: Fix int_SI_fs_interp_constantMichel Danzer
The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-1480-colNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma
This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao
inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune
It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175183 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Export instructions are no longer terminatorVincent Lejeune
This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175182 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Fold zero/one in export instructionsVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Do not fold modifier/litterals in vector instVincent Lejeune
This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: switch from neverHasSideEffects to hasSideEffects.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175173 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: stop claiming that NEON registers are usable for now.Tim Northover
If vector types have legal register classes, then LLVM bypasses LegalizeTypes on them, which causes faults currently since the code to handle them isn't in place. This fixes test failures when AArch64 is the default target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: add block comments where missingTim Northover
Only comments affected. No code change at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Workaround an MSan false positive.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Add some legality checks for SETCC before introducing it in the DAG combiner ↵Owen Anderson
post-operand legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175149 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky
Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer
Fixes assertion failure in newly added lit test. Might just be a bandaid that needs to be revisited. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175139 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14RegisterCoalescer::reMaterializeTrivialDef() can constrain the destinationCameron Zwarich
register class to match the defining instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Teach the DataLayout aware constant folder to be much more aggressive towardsNick Lewycky
'and' instructions. This is a pattern that shows up a lot in ubsan binaries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Remove the form field from Mips16 instruction formats and set thingsReed Kotler
up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fix RegisterCoalescer::rematerializeTrivialDef() so that it works on flippedCameron Zwarich
CoalescerPairs. Also, make it take a CoalescerPair directly like other methods of RegisterCoalescer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fix some issues with rematerialization in RegisterCoalescer when the destinationCameron Zwarich
of the copy is a subregister def. The current code assumes that it can do a full def of the destination register, but it is not checking that the def operand is read-undef. It also doesn't clear the subregister index of the destination in the new instruction to reflect the full subregister def. These issues were found running 'make check' with my next commit that enables rematerialization in more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Don't assume the mangling of static functions.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175121 91177308-0d34-0410-b5e6-96231b3b80d8
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