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MCAsmLayout object.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
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and defining the add pattern with Pat<>, eliminating a use of
parallel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99375 91177308-0d34-0410-b5e6-96231b3b80d8
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respectively, and add some more comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99372 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99370 91177308-0d34-0410-b5e6-96231b3b80d8
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ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99360 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99359 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99358 91177308-0d34-0410-b5e6-96231b3b80d8
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test run permformance numbers say as to whether it helps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
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domain crossings."
This reverts commit 99345. It was breaking buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99352 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99350 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99348 91177308-0d34-0410-b5e6-96231b3b80d8
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just use an empty result list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
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crossings.
This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99345 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
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for the noinline attribute, and make the inliner refuse to
inline a call site when the call site is marked noinline even
if the callee isn't. This fixes PR6682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99341 91177308-0d34-0410-b5e6-96231b3b80d8
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needed here.
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beyond just calling getTypeToTransformTo.
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for ignoring debug info intrinsics everywhere else is to advance
past them, and it needs to be consistent.
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patch by Alex Mac!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8
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Converted some of the NEON vcvt instructions to this format.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99324 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
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MachineBasicBlock::iterator that does this automatically?
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
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Ref: A7.4.6 One register and a modified immediate value.
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optimizations down stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99282 91177308-0d34-0410-b5e6-96231b3b80d8
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if Function::hasAddressTaken works as advertised
also included some cosmetic cleanups
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
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transformations.
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
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Also, both MCMachOStreamer and MCAssembler are now target independent!
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particular instruction + fixups might need relaxation.
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dependencies in MCMachOStreamer and MCAssembler.
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implementation.
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don't need to recompute them during relaxation. I will revisit this once all the other pieces of fast relaxation are in place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99227 91177308-0d34-0410-b5e6-96231b3b80d8
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