aboutsummaryrefslogtreecommitdiff
path: root/lib
AgeCommit message (Collapse)Author
2012-01-11Hoist the logic to transform shift+mask combinations into sub-registerChandler Carruth
extracts and scaled addressing modes into its own helper function. No functionality changed here, just hoisting and layout fixes falling out of that hoisting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Teach the X86 instruction selection to do some heroic transforms toChandler Carruth
detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Improved compile time:Stepan Dyatkovskiy
1. Size heuristics changed. Now we calculate number of unswitching branches only once per loop. 2. Some checks was moved from UnswitchIfProfitable to processCurrentLoop, since it is not changed during processCurrentLoop iteration. It allows decide to skip some loops at an early stage. Extended statistics: - Added total number of instructions analyzed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Clarified the SCEV getSmallConstantTripCount interface with in-your-face ↵Andrew Trick
comments. This interface is misleading and dangerous, but it is actually what we need for unrolling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Add big endian mips support. Based on a patch by Jack Carter.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Add the skeleton of an asm parser for mips.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147923 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11ARM Ld/St Optimizer fix.Andrew Trick
Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Detect when a value is undefined on an edge to a landing pad.Jakob Stoklund Olesen
Consider this code: int h() { int x; try { x = f(); g(); } catch (...) { return x+1; } return x; } The variable x is undefined on the first edge to the landing pad, but it has the f() return value on the second edge to the landing pad. SplitAnalysis::getLastSplitPoint() would assume that the return value from f() was live into the landing pad when f() throws, which is of course impossible. Detect these cases, and treat them as if the landing pad wasn't there. This allows spill code to be inserted after the function call to f(). <rdar://problem/10664933> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Exclusively use SplitAnalysis::getLastSplitPoint().Jakob Stoklund Olesen
Delete the alternative implementation in LiveIntervalAnalysis. These functions computed the same thing, but SplitAnalysis caches the result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147911 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Avoid CSE of instructions which define physical registers across MBBs unlessEvan Cheng
the physical registers are not allocatable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11If the global variable is removed by the linker, then don't constant merge itBill Wendling
with other symbols. An object in the __cfstring section is suppoed to be filled with CFString objects, which have a pointer to ___CFConstantStringClassReference followed by a pointer to a __cstring. If we allow the object in the __cstring section to be merged with another global, then it could end up in any section. Because the linker is going to remove these symbols in the final executable, we shouldn't bother to merge them. <rdar://problem/10564621> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Don't avoid recursing for pointer types, just reference types. Expand onEric Christopher
the comment. Fixes constvars.exp on the gdb test builder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fixed order of operands in comment to match code.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.Joerg Sonnenberger
Add a test that checks the stack alignment of a simple function for Darwin, Linux and NetBSD for 32bit and 64bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Consider unknown alignment caused by OptimizeThumb2Instructions().Jakob Stoklund Olesen
This function runs after all constant islands have been placed, and may shrink some instructions to their 2-byte forms. This can actually cause some constant pool entries to move out of range because of growing alignment padding. Treat instructions that may be shrunk the same as inline asm - they erode the known alignment bits. Also reinstate an old assertion in verify(). It is correct now that basic block offsets include alignments. Add a single large test case that will hopefully exercise many parts of the constant island pass. <rdar://problem/10670199> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-1080 col violation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a fewChad Rosier
failing test cases on our internal AVX nightly tester. rdar://10663637 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Let asm parser query asm syntax dialect.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10This is the matching change for the data structure name changes for theKevin Enderby
functional change in r147860 to use DW_TAG_label's instead TAG_subprogram's. This only changes names and updates comments. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach
rdar://10663487 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix some leftover control reaches end of non-void function warnings.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Teach the triple library about the androideabi environment.Chandler Carruth
Patch by Evgeniy Stepanov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147871 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Move default case for covered enum outside of switch.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147870 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10For i386, don't use the generic code.Bill Wendling
As the comment around 7746 says, it's better to use the x87 extended precision here than SSE. And the generic code doesn't know how to do that. It also regains the speed lost for the uint64_to_float.c testcase. <rdar://problem/10669858> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a -Wreturn-type warning in g++.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Cleanup these asserts to follow common LLVM style and codingChandler Carruth
conventions. Also, clarify the grouping of one of the asserts to silence -Wparentheses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth
of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Various crash reporting tools have a problem with the dwarf generated forKevin Enderby
assembly source when it generates the TAG_subprogram dwarf debug info for the labels that have nothing between them as in this bit of assembly source: % cat ZeroLength.s _func1: _func2: nop One solution would be to not emit the subsequent labels with the same address and use the next label with a different address or the end of the section for the AT_high_pc value of the TAG_subprogram. Turns out in llvm-mc it is not possible in all cases to determine of two symbols have the same value at the point we put out the TAG_subprogram dwarf debug info. So we will have llvm-mc instead of putting out TAG_subprogram's put out DW_TAG_label's. And the DW_TAG_label does not have a AT_high_pc value which avoids the problem. This commit is only the functional change to make the diffs clear as to what is really being changed. The next commit will be to clean up the names of such things like MCGenDwarfSubprogramEntry to something like MCGenDwarfLabelEntry. rdar://10666925 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add definition for intel asm variant.Devang Patel
Right now, this just adds additional entries in match table. The parser does not use them yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove unnecessary default cases in switches that cover all enum values.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem
using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add definitions for AMD's bobcat (aka btver1)Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. ↵Craig Topper
There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is ↵Craig Topper
the final piece to remove the AVX hack that disabled SSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. ↵Craig Topper
AVX is now an SSE level and no longer disables SSE checks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper
predicates. Another commit will remove orAVX functions from X86SubTarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng
define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Enable LSR IV Chains with sufficient heuristics.Andrew Trick
These heuristics are sufficient for enabling IV chains by default. Performance analysis has been done for i386, x86_64, and thumbv7. The optimization is rarely important, but can significantly speed up certain cases by eliminating spill code within the loop. Unrolled loops are prime candidates for IV chains. In many cases, the final code could still be improved with more target specific optimization following LSR. The goal of this feature is for LSR to make the best choice of induction variables. Instruction selection may not completely take advantage of this feature yet. As a result, there could be cases of slight code size increase. Code size can be worse on x86 because it doesn't support postincrement addressing. In fact, when chains are formed, you may see redundant address plus stride addition in the addressing mode. GenerateIVChains tries to compensate for the common cases. On ARM, code size increase can be mitigated by using postincrement addressing, but downstream codegen currently misses some opportunities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Accurately model hardware alignment rounding.Jakob Stoklund Olesen
On Thumb, the displacement computation hardware uses the address of the current instruction rouned down to a multiple of 4. Include this rounding in the UserOffset we compute for each instruction. When inline asm is present, the instruction alignment may not be known. Constrain the maximum displacement instead in that case. This makes it possible for CreateNewWater() and OffsetIsInRange() to agree about the valid displacements. When they disagree, infinite looping happens. As always, test cases for this stuff are insane. <rdar://problem/10660175> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove the logging streamer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Catch runaway ARMConstantIslandPass even in -Asserts builds.Jakob Stoklund Olesen
The pass is prone to looping, and it is better to crash than loop forever, even in a -Asserts build. <rdar://problem/10660175> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Fix asm string wrt variants.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Adding IV chain generation to LSR.Andrew Trick
After collecting chains, check if any should be materialized. If so, hide the chained IV users from the LSR solver. LSR will only solve for the head of the chain. GenerateIVChains will then materialize the chained IV users by computing the IV relative to its previous value in the chain. In theory, chained IV users could be exposed to LSR's solver. This would be considerably complicated to implement and I'm not aware of a case where we need it. In practice it's more important to intelligently prune the search space of nontrivial loops before running the solver, otherwise the solver is often forced to prune the most optimal solutions. Hiding the chained users does this well, so that LSR is more likely to find the best IV for the chain as a whole. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Adding collection of IV chains to LSR.Andrew Trick
This collects a set of IV uses within the loop whose values can be computed relative to each other in a sequence. Following checkins will make use of this information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel
AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09"Minor LSR debugging stuff"Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Update language check. Do not ignore DW_LANG_Python.Devang Patel
Patch by Joe Groff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Move assert to the right place.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09InstCombine: Teach foldLogOpOfMaskedICmpsHelper that sign bit tests are bit ↵Benjamin Kramer
tests. This subsumes several other transforms while enabling us to catch more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Don't rely on the fact that shift values are never very large, and thusChandler Carruth
this substraction will result in small negative numbers at worst which become very large positive numbers on assignment and are thus caught by the <=4 check on the next line. The >0 check clearly intended to catch these as negative numbers. Spotted by inspection, and impossible to trigger given the shift widths that can be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147773 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 19:28:44 +0000