aboutsummaryrefslogtreecommitdiff
path: root/lib
AgeCommit message (Collapse)Author
2011-12-21ARM assembly parsing allows constant expressions for lane indices.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Fix bug in zero-store peephole pattern reported in pr11615.Akira Hatanaka
The patch and test case were originally written by Mans Rullgard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Expand 64-bit CTLZ nodes if target architecture does not support it. Add testAkira Hatanaka
case for DCLO and DCLZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Expand 64-bit CTPOP and CTTZ.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Expand 64-bit atomic load and store.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add definition of DSBH (Double Swap Bytes within Halfwords) and Akira Hatanaka
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add definition of WSBH (Word Swap Bytes within Halfwords), which is anAkira Hatanaka
instruction supported by mips32r2, and add a pattern which replaces bswap with a ROTR and WSBH pair. WSBW is removed since it is not an instruction the current architectures support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-2064-bit uint-fp conversion nodes are expanded.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Enable custom lowering DYNAMIC_STACKALLOC nodes.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Set the correct stack pointer register that should be saved or restored.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Fix a nasty bug in the type remapping stuff that I added that is breaking ↵Chris Lattner
kc++ on the build bot in some cases. The basic issue happens when a source module contains both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if the destination module contains a "%foo" type, and it will return true... because both the source and destination modules are in the same LLVMContext. We don't want to map source types to other source types, so don't do the remapping if the mapped type came from the source module. Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is pretty great that way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM .req register name aliases are case insensitive, just like regnames.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add function MipsDAGToDAGISel::SelectMULT and factor out code that generatesAkira Hatanaka
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Fix indentation.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-2064-bit data directive.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-2032-to-64-bit sext_inreg pattern.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add 64-bit extload patterns.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add patterns for matching extloads with 64-bit address. The patterns are enabledAkira Hatanaka
only when the target ABI is N64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Move comment to appropriate place.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add code in MipsDAGToDAGISel for selecting constant +0.0.Akira Hatanaka
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Heed spill slot alignment on ARM.Jakob Stoklund Olesen
Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Revert part of r146995 that was accidentally commmitted.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-2032-to-64-bit sign extension pattern.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add a pattern for matching zero-store with 64-bit address. The pattern is ↵Akira Hatanaka
enabled only when the target ABI is N64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM assembly parsing and encoding for VST2 single-element, double spaced.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Fix assert condition.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add support to add named metadata operand.Devang Patel
Patch by Andrew Wilkins! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146984 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM assembly parsing and encoding for VLD2 single-element, double spaced.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20First steps in ARM AsmParser support for .eabi_attribute and .archJason W Kim
(Both used for Linux gnueabi) No behavioral change yet (no tests need so far) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20This is the second fix related to VZEXT_MOVL node.Elena Demikhovsky
The failure that I see in the current version is: LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14] 0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13] 0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12] 0x18b9870: v4i64 = undef [ID=4] 0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10] 0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9970: i32 = Constant<0> [ID=3] 0x18b9170: v2i64 = undef [ORD=1] [ID=1] 0x18b9570: i32 = Constant<2> [ID=5] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Begin teaching the X86 target how to efficiently codegen patterns thatChandler Carruth
use the zero-undefined variants of CTTZ and CTLZ. These are just simple patterns for now, there is more to be done to make real world code using these constructs be optimized and codegen'ed properly on X86. The existing tests are spiffed up to check that we no longer generate unnecessary cmov instructions, and that we generate the very important 'xor' to transform bsr which counts the index of the most significant one bit to the number of leading (most significant) zero bits. Also they now check that when the variant with defined zero result is used, the cmov is still produced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Fixes a potential compilation error.Manuel Klimek
Pulling the template implementation into the header to guarantee that it's visible to all possible instantiations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Pulls the implementation of skip() into JSONParser.Manuel Klimek
This is the first step towards migrating more of the parser implementation into the parser class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Addressing style issues in JSON parser.Manuel Klimek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Fix up the CMake build for the new files added in r146960, they'reChandler Carruth
likely to stay either way that discussion ends up resolving itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Unweaken vtables as per ↵David Blaikie
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20LSR: Fix another corner case in expansion of postinc users.Andrew Trick
Fixes PR11571: Instruction does not dominate all uses git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146950 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function with setjmp/longjmp exception handling clobbers all the registers. But with the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are expanded away earlier, before PEI can see them to determine what registers to save and restore. Mark the dispatchsetup instruction in the same way, since that instruction cannot be expanded early. This also more accurately reflects when the registers are clobbered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Now that PR11464 is fixed, reapply the patch to fix PR11464, Chris Lattner
merging types by name when we can. We still don't guarantee type name linkage but we do it when obviously the right thing to do. This makes LTO type names easier to read, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20fix PR11464 by preventing the linker from mapping two different struct types ↵Chris Lattner
from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add basic generic CodeGen support for half.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.Jim Grosbach
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117" rdar://10603913 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach
rdar://9932658 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19Add a if-conversion optimization that allows 'true' side of a diamond to beEvan Cheng
unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19Add patterns for matching immediates whose lower 16-bit is cleared. TheseAkira Hatanaka
patterns emit a single LUi instruction instead of a pair of LUi and ORi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19Attempt to fix PR11607 by shuffling around which class defines which methods.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146897 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 04:00:09 +0000