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2012-01-06Fix uninitialized variable warning.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Fix a leak I noticed while reviewing the accelerator table changes. PassesEric Christopher
lldb testsuite. rdar://10652330 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06[asan] cleanup: remove the SIGILL-related code (compiler part)Kostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Fix typo in stringEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06As part of the ongoing work in finalizing the accelerator tables, extendEric Christopher
the debug type accelerator tables to contain the tag and a flag stating whether or not a compound type is a complete type. rdar://10652330 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Fix SpeculativelyExecuteBB to either speculate all or none of the phisDan Gohman
present in the bottom of the CFG triangle, as the transformation isn't ever valuable if the branch can't be eliminated. Also, unify some heuristics between SimplifyCFG's multiple if-converters, for consistency. This fixes rdar://10627242. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05PR11705, part 2: globalopt shouldn't put inttoptr/ptrtoint operations into ↵Eli Friedman
global initializers if there's an implied extension or truncation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Link symbols with different visibilities according to the rules in theRafael Espindola
System V Application Binary Interface. This lets us use -fvisibility-inlines-hidden with LTO. Fixes PR11697. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Revert r56315. When the instruction to speculate is a load, thisDan Gohman
code can incorrectly move the load across a store. This never happens in practice today, but only because the current heuristics accidentally preclude it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Kill ObjectCodeEmitter and BinaryObject, they were unused and superseded by MC.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05SCCCaptured is trivially false on entry to this loop and not modified inside it.Nick Lewycky
Eliminate the dead test for it on each loop iteration. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Remove the old ELF writer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05A small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be ↵Danil Malyshev
called with the base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05revert r147542 after comments from Joerg SonnenbergerSebastian Pop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Remove an unused variable.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147605 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Prevent a DAGCombine from firing where there are two uses ofChandler Carruth
a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Mark scalar FMA4 instructions as ignoring the VEX.L bit.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Peephole optimization of ptest-conditioned branch in X86 arch. Performs ↵Victor Umansky
instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX. Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX) Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Minor postra scheduler cleanup. It could result in more precise ↵Andrew Trick
antidependence latency on ARM in exceedingly rare cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Replace the uint64_t -> double convertion algorithm with one that's more ↵Bill Wendling
efficient. This small bit of ASM code is sufficient to do what the old algorithm did: movq %rax, %xmm0 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } #ifdef __SSE3__ haddpd %xmm0, %xmm0 #else pshufd $0x4e, %xmm0, %xmm1 addpd %xmm1, %xmm0 #endif It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on all processors. <rdar://problem/7719814> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen
Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Avoid reserving an ARM base pointer during register allocation.Jakob Stoklund Olesen
Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen
The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Generalize isSafeToSpeculativelyExecute to work on arbitraryDan Gohman
Values, rather than just Instructions, since it's interesting for ConstantExprs too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Silence warnings of a mysterious compiler that still defaults to C89.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJITSebastian Pop
Get back getHostTriple. For JIT compilation, use the host triple instead of the default target: this fixes some JIT testcases that used to fail when the compiler has been configured as a cross compiler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Enable -soft-float for MIPS.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Remove pointless asserts.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Teach instcombine all sorts of great stuff about shifts that have exact, nuw orNick Lewycky
nsw bits on them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper
are commuted in the shuffle mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Rename immLUiOpnd.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04- Define base classes for Jump-and-link instructions and make 32-bit and 64-bitAkira Hatanaka
versions derive from them. - JALR64 is not needed since N64 does not emit jal. - Add template parameter to BranchLink that sets the rt field. - Fix the set of temporary registers for O32 and N64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Have getRegForInlineAsmConstraint return the correct register class when targetAkira Hatanaka
is Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Fix more places which should be checking for iOS, not darwin.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04For x86, canonicalize maxEvan Cheng
(x > y) ? x : y => (x >= y) ? x : y So for something like (x - y) > 0 : (x - y) ? 0 It will be (x - y) >= 0 : (x - y) ? 0 This makes is possible to test sign-bit and eliminate a comparison against zero. e.g. subl %esi, %edi testl %edi, %edi movl $0, %eax cmovgl %edi, %eax => xorl %eax, %eax subl %esi, $edi cmovsl %eax, %edi rdar://10633221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147512 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner
Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03generalize LLVMContext::emitError to take a twine instead of a StringRef.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Fix 80-column violations.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen
This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Assert when reserved registers have been assigned.Jakob Stoklund Olesen
This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Revert 147426 because it caused pr11696.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem
integer-promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Enhance DAGCombine for transforming 128->256 casts into a vmovaps, ratherChad Rosier
then a vxorps + vinsertf128 pair if the original vector came from a load. rdar://10594409 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147481 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Conform to the style guide; remove 'else' after 'return'. Also remove an extraNick Lewycky
if-statement by turning it into an assert. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147474 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson
Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147472 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Clarified assert text.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Fix malformed assert.Matt Beaumont-Gay
If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Fix typo in ruler. No functionality change.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Intel style asm variant does not need '%' prefix.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147453 91177308-0d34-0410-b5e6-96231b3b80d8
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