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table size.
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after using bugpoint to reduce the confusion presented by the original names, which no longer mean what they used to.
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Factor similar code out of FNEG DAG combiner.
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Patch by Brad Smith!
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The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.
For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.
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right now. We'll fix PR13303 a different way.
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and InlineAsmVariant don't match.
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and update the printOperand() function accordingly.
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The ARM backend can eliminate cmp instructions by reusing flags from a
nearby sub instruction with similar arguments.
Don't do that if the sub is predicated - the flags are not written
unconditionally.
<rdar://problem/12263428>
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properly.
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- Fix an remaining issue of PR11674 as well
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Improve AQ instruction selection in the Hexagon MI scheduler.
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This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs).
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- If a boolean value is generated from CMOV and tested as boolean value,
simplify the use of test result by referencing the original condition.
RDRAND intrinisc is one of such cases.
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concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types.
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intervals twice or to theirself.
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single basic block.
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undefined or zeroinitializer.
I've added the "zeroinitializer" case in this patch.
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- The C API should be stable
- InlineAsm::AsmDialect is not exposed to C
- The function didn't match the prototype so this was unreachable code
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region.
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during critical edge splitting.
Previously we checked if the register is def'd in a block via the def/use list a
nd walked the list of kills to check if the register is killed in a block. Both
of these checks can be made much cheaper by walking the block first and
recording all defs and kills.
This reduces the compile time of the test case from PR13651 from 40s to 15s at
-O2. The compile time is still dominated by LV updating but now the main culprit
is SparseBitVector's slowness.
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FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct.
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