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2011-04-05Do not emit empty name.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Added *hidden* flags -print-options and -print-all-options soAndrew Trick
developers can see if their driver changed any cl::Option's. The current implementation isn't perfect but handles most kinds of options. This is nice to have when decomposing the stages of compilation and moving between different drivers. It's also a good sanity check when comparing results produced by different command line invocations that are expected to produce the comparable results. Note: This is not an attempt to prolong the life of cl::Option. On the contrary, it's a placeholder for a feature that must exist when cl::Option is replaced by a more appropriate framework. A new framework needs: a central option registry, dynamic name lookup, non-global containers of option values (e.g. per-module, per-function), *and* the ability to print options values and their defaults at any point during compilation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05An MCDisassembler has the option to not implementShantonu Sen
getEDInfo(), in which case this code would dereference NULL. EDInst can already handle NULL info, so avoid the dereference and pass NULL through. Reviewed by Sean Callanan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Make second source operand of LDRD pre/post explicit.Jim Grosbach
Finish what r128736 started. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Constants with multiple encodings (ARM):Johnny Chen
An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Check for invalid register encodings for UMAAL and friends where:Johnny Chen
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson
ADC/ABC with the appropriate S-bit input value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen
addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Print visibility info for external variables.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Use std::unique instead of a SmallPtrSet to ensure unique instructions in ↵Jakob Stoklund Olesen
UseSlots. This allows us to always keep the smaller slot for an instruction which is what we want when a register has early clobber defines. Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away addressNadav Rotem
space info. We crash with an assert in this case. This change checks that the address space of the bitcasted pointer is the same as the gep ptr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Stop precomputing last split points, query the SplitAnalysis cache on demand.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Cache the fairly expensive last split point computation and provide a fastJakob Stoklund Olesen
inlined path for the common case. Most basic blocks don't contain a call that may throw, so the last split point os simply the first terminator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling
It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Just use BL all the time. It's safer that way.Eric Christopher
Fixes rdar://9184526 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Revert 123704; it broke threaded LLVM.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Fix SRS/SRSW encoding bits.Johnny Chen
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04A8.6.105 MULJohnny Chen
Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04RFE encoding should also specify the "should be" encoding bits.Johnny Chen
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Add missing file from r128851.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Layer the memory manager between the JIT and the runtime Dyld.Jim Grosbach
The JITMemory manager references LLVM IR constructs directly, while the runtime Dyld works at a lower level and can handle objects which may not originate from LLVM IR. Introduce a new layer for the memory manager to handle the interface between them. For the MCJIT, this layer will be almost entirely simply a call-through w/ translation between the IR objects and symbol names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Make OpcodeMask an unsigned long long literal to deal with overflow.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Allow coalescing with reserved physregs in certain cases:Jakob Stoklund Olesen
When a virtual register has a single value that is defined as a copy of a reserved register, permit that copy to be joined. These virtual register are usually copies of the stack pointer: %vreg75<def> = COPY %ESP; GR32:%vreg75 MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill> MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0 MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0 CALLpcrel32 ... Coalescing these virtual registers early decreases register pressure. Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after register allocation was completed. The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail because it depends on linear scan spilling a particular register. I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of instructions emitted, and its revision history shows the 'correct' count being edited many times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Extract physreg joining policy to a separate method.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen
rdar://problem/9225433 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Insert code in the right location when lowering PowerPC atomics.Jakob Stoklund Olesen
This causes defs to dominate uses, no instructions after terminators, and other goodness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes
also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Move transformation of JmpLink and related nodes done during instruction ↵Akira Hatanaka
selection to Legalize phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04PowerPC atomic pseudos clobber CR0, they don't read it.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Use X0 instead of R0 for the zero register on ppc64.Jakob Stoklund Olesen
The 32-bit R0 cannot be used where a 64-bit register is expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Add support for the VIA PadLock instructions.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Expand Op0Mask by one bit in preparation for the PadLock prefixes.Joerg Sonnenberger
Define most shift masks incrementally to reduce the redundant hard-coding. Introduce new shift for the VEX flags to replace the magic constant 32 in various places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Stop caching basic block index ranges now that SlotIndexes can keep up.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Delete leftover data members.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Remove some support for ReturnInsts with multiple operands, and forJay Foad
returning a scalar value in a function whose return type is a single- element structure or array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Region: Allow user control the printing style of the print function.Tobias Grosser
Contributed by: etherzhhb@gmail.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128808 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Attempt to fix breakage from r128782 reported by Francois Pichet onEli Friedman
llvm-commits. (Not sure why it only breaks on Windows; maybe it has something to do with the iterator representation...) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-03Start migrating mach-o dumping facilities to the object file out of aEric Christopher
separate executable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-03Move Object.cpp out of VMCore and into Object.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128800 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-03Assorted bugfixes in object file handling:Eric Christopher
- Adds support for sniffing PE/COFF files on win32 (.exe and .dll) which are COFF files that have an MS-DOS compatibility stub on the front of them. - Fixes a bug in the COFFObjectFile's support for the Microsoft COFF extension for long symbol names, wherein it was attempting to parse the leading '/' in an extended symbol name reference as part of the integer offset. - Fixes bugs in COFFObjectFile and ELFObjectFile wherein section and symbol iterators were being returned with uninitialized bytes; the type DataRefImpl is a union between 2 32-bit words (d.a and d.b) and a single intptr_t word (p). Only p was being initialized, so in 32-bit builds the result would be iterators with random upper 32-bit words in their DataRefImpls. This caused random failures when seeking around in object files. Patch by Graydon Hoare! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128799 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-03Add a set of C bindings for the Object interface.Eric Christopher
Patch by Patrick Walton! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instructionEli Friedman
after the given instruction; make sure to handle that case correctly. (It's difficult to trigger; the included testcase involves a dead block, but I don't think that's a requirement.) While I'm here, get rid of the unnecessary warning about SimplifyInstructionsInBlock, since it should work correctly as far as I know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Don't assume something which might be a constant expression is an instruction.Eli Friedman
Based on PR9429, but no testcase because I can't figure out how to trigger it anymore given other changes to the relevant code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02While SimplifyDemandedBits constant folds this, we can't rely on it here.Benjamin Kramer
It's possible to craft an input that hits the recursion limits in a way that SimplifyDemandedBits doesn't simplify the icmp but ComputeMaskedBits can infer which bits are zero. No test case as it depends on too many other things. Fixes PR9609. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02ptx: support setp's 4-operand formatChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Use InterferenceCache in RegAllocGreedy.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Add an InterferenceCache class for caching per-block interference ranges.Jakob Stoklund Olesen
When the greedy register allocator is splitting multiple global live ranges, it tends to look at the same interference data many times. The InterferenceCache class caches queries for unaltered LiveIntervalUnions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Use basic block numbers as indexes when mapping slot index ranges.Jakob Stoklund Olesen
This is more compact and faster than using DenseMap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich
registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
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