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2010-11-02Remove an assert - it's possible to be hit, and we just want to avoidEric Christopher
handling those cases for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02WhitespeaceEric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02No really, no thumb1 for arm fast isel. Also add an informative comment asEric Christopher
to what someone would need to do to support thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Don't try to split weird critical edges that really aren't:Jakob Stoklund Olesen
BB#1: derived from LLVM BB %bb.nph28 Live Ins: %AL Predecessors according to CFG: BB#0 TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384 JNE_4 <BB#2>, %EFLAGS<imp-use,kill> JMP_4 <BB#2> Successors according to CFG: BB#2 BB#2 These double CFG edges only ever occur in bugpoint-generated code, so there is no need to attempt something clever. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Attempt to provide correct encodings for a number of other vld1 variants, ↵Owen Anderson
which we can't test since we can neither generate nor parse them at the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117988 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Add aesthetic break.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117986 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01MachineLICM should not claim to be preserving the CFG when it can split criticalJakob Stoklund Olesen
edges on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Be more precise about verifying missing kill flags.Jakob Stoklund Olesen
It is legal for an instruction to have two operands using the same register, only one a kill. This is interpreted as a kill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01When inserting copies during splitting, always use the parent register as theJakob Stoklund Olesen
source, and let rewrite() clean it up. This way, kill flags on the inserted copies are fixed as well during rewrite(). We can't just assume that all the copies we insert are going to be kills since critical edges into loop headers sometimes require both source and dest to be live out of a block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXMEJim Grosbach
for handling the fixup necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Remove unused function.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add support for alignment operands on VLD1-lane instructions.Bob Wilson
This is another part of the fix for Radar 8599955. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Missed reverting this bit.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Minor cleanup.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01rearrange a bit.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add kill flag verification.Jakob Stoklund Olesen
At least X86FloatingPoint requires correct kill flags after register allocation, and targets using register scavenging benefit. Conservative kill flags are not enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Update kill flags while rewriting instructions after splitting.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117959 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Move the machine operand MC encoding patterns to the parent classes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117956 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01When folding away a (shl (shr)) pair, we need to check that the bits that ↵Owen Anderson
will BECOME the low bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01use our fancy new MnemonicAlias mechanism to remove a bunch of hacksChris Lattner
from X86AsmParser.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling
at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Don't assign new registers created during a split to the same stack slot, butJakob Stoklund Olesen
give them individual stack slots once the are actually spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add basic LiveStacks verification.Jakob Stoklund Olesen
When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01NEON does not support truncating vector stores. Radar 8598391.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add FIXME.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gatesJim Grosbach
codegen using the patterns; the latter gates the assembler recognizing the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Write the line info to .debug_line.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Mark ARM subtarget features that are available for the assembler.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01The T2 extract/pack instructions are only valid in Thumb2 mode. Mark theJim Grosbach
patterns as such git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add support for .value.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Implement .weakref.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Move instruction encoding bits into the parent class and remove the temporaryBill Wendling
*_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01The testcase is now XFAILed. Sorry about the breakage.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01"mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner
must be 8 bits. Support this memory form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Implement enough of the missing instalias support to getChris Lattner
aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01make the asm matcher emitter reject instructions that have commentsChris Lattner
in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01reject instructions that contain a \n in their asmstring. MarkChris Lattner
various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Revert r117876 for now, it's causing more testsuite failures.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling
looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner
Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner
and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31reapply r117858 with apparent editor malfunction fixed (somehow I Chris Lattner
got a dulicated line). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31revert r117858 while I check out a failure I missed.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31the asm matcher can't handle operands with modifiers (like ${foo:bar}).Chris Lattner
Instead of silently ignoring these instructions, emit a hard error and force the target author to either refactor the target or mark the instruction 'isCodeGenOnly'. Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are doing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner
how the push/pop mnemonic aliases are wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
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