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2010-03-26Try trivial remat before the coalescer gives up on a vr / physreg coalescing ↵Evan Cheng
for fear of tying up a physical register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99575 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-26Handle DEBUG_VALUE in this pass.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach
Re-commit. This time complete with testsuite updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25need to fix 'make check' tests first. revert for a moment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25switch the flag for using NEON for SP floating point to a subtarget 'feature'Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25rename pred_const_iterator to const_pred_iterator for consistency's sakeGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Removed instruction class NI from ARMInstrFormats.td.Johnny Chen
It doesn't seem to be used anywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25switch the use-vml[as] instructions flag to a subtarget 'feature'Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25rename use_const_iterator to const_use_iterator for consistency's sakeGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25llvm-mc: Add a -mc-relax-all option, which relaxes every fixup. We always needDaniel Dunbar
exactly two passes in that case, and don't ever need to recompute any layout, so this is a nice baseline for relaxation performance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Add NVDupLnFrm and change NVDupLane class to use that format.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpuJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm toJohnny Chen
expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Code clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99544 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Stop restarting layout on every relaxation.Daniel Dunbar
- Still O(N^2), just a faster form, and now its the MCAsmLayout's fault. On the .s I am tuning against (combine.s from 403.gcc): -- ddunbar@lordcrumb:MC$ diff stats-before.txt stats-after.txt 5,10c5,10 < 1728 assembler - Number of assembler layout and relaxation steps < 7707 assembler - Number of emitted assembler fragments < 120588 assembler - Number of emitted object file bytes < 2233448 assembler - Number of evaluated fixups < 1727 assembler - Number of relaxed instructions < 6723845 mcexpr - Number of MCExpr evaluations --- > 3 assembler - Number of assembler layout and relaxation steps > 7707 assembler - Number of emitted assembler fragments > 120588 assembler - Number of emitted object file bytes > 14796 assembler - Number of evaluated fixups > 1727 assembler - Number of relaxed instructions > 67889 mcexpr - Number of MCExpr evaluations -- Feel free to LOL at the -before numbers, if you like. I am a little surprised we make more than 2 relaxation passes. It's pretty trivial for us to do relaxation out-of-order if that would give a speedup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99543 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Fix -Asserts warning, again.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99542 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Tag SSE2 integer instructions as SSEPackedInt.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Teach TableGen to understand X.Y notation in the TSFlagsFields strings.Jakob Stoklund Olesen
Remove much horribleness from X86InstrFormats as a result. Similar simplifications are probably possible for other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25fix a valgrind error on copy-constructor-synthesis.cpp, which is caused whenChris Lattner
the custom insertion hook deletes the instruction, then we try to set dead flags on it. Neither the code that I added nor the code that was there before was safe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Remove an unused option.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Simplify main section layout process by moving alignment into LayoutSection.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Sink Section address assignment into LayoutSection.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99528 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain ↵Jakob Stoklund Olesen
crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,Johnny Chen
instead of the current N2V. Format of NVDupLane instances are set to NEONFrm currently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Reapply Kevin's change 94440, now that Chris has fixed the limitation onBob Wilson
opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Add comment.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC/Mach-O: Switch to MCSectionData::getOrdinal.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Scheduler assumes SDDbgValue nodes are in source order. That's true ↵Evan Cheng
currently. But add an assertion to verify it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Explicity track section and fragment ordinals.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Fix -Asserts warning.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Change tblgen to emit FOOISD opcode names as twoChris Lattner
bytes instead of one byte. This is important because we're running up to too many opcodes to fit in a byte and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE making the numbering sparse. This just bites the bullet and bloats out the table. In practice, this increases the size of the x86 isel table from 74.5K to 76K. I think we'll cope :) This fixes rdar://7791648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Include isFunctionLocal while calculating folding node set profile for a MDNode.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99490 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Remove a fixme that doesn't make sense any more.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25fix PR6642, GVN forwarding from memset to load of the base of the memset.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Make sure SDDbgValue.Invalid is initialized to false by all the constructors.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25eliminate a bunch more parallels now that schedulingChris Lattner
handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Make the NDEBUG assertion stronger and more clear what is Chris Lattner
happening. Enhance scheduling to set the DEAD flag on implicit defs more aggressively. Before, we'd set an implicit def operand to dead if it were present in the SDNode corresponding to the machineinstr but had no use. Now we do it in this case AND if the implicit def does not exist in the SDNode at all. This exposes a couple of problems: one is the FIXME, which causes a live intervals crash on CodeGen/X86/sibcall.ll. The second is that it makes machinecse and licm more aggressive (which is a good thing) but also exposes a case where licm hoists a set0 and then it doesn't get resunk. Talking to codegen folks about both these issues, but I need this patch in in the meantime. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Include isFunctionLocal while calculating folding node set provide for a MDNode.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Reapply r99451 with a fix to move the NoInline check to the cost functionsEric Christopher
instead of InlineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25reapply 99444/99445, which I speculatively reverted inChris Lattner
r99453. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Route access to SectionData offset and file size through MCAsmLayout.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Route access to Fragment offset and effective size through MCAsmLayout.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Change how dbg_value sdnodes are converted into machine instructions. Their ↵Evan Cheng
placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. Here is a theoretical example that illustrates why the placement is important. tmp1 = store tmp1 -> x ... tmp2 = add ... ... call ... store tmp2 -> x Now mem2reg comes along: tmp1 = dbg_value (tmp1 -> x) ... tmp2 = add ... ... call ... dbg_value (tmp2 -> x) When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1. Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers"). This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Eliminate MC{Fragment,{Section,Symbol}Data}::getAddress.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25MC: Fix refacto in MCExpr evaluation, I mistakenly replaced a fragment ↵Daniel Dunbar
address with a symbol address. - This fixes the integrated-as nightly test regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Avoid being influenced by dbg_value instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Disable folding loads into tail call in 32-bit PIC mode. It can introduce ↵Evan Cheng
illegal code like this: addl $12, %esp popl %esi popl %edi popl %ebx popl %ebp jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class. The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24revert 99444/99445. This doesn't cause the failure of Chris Lattner
2006-07-19-stwbrx-crash.ll for me, but it's the only likely patch in the blame list of several bots. Lets see if this fixes it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24Temporarily revert this, it's causing an issue with an internal project.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24Speculatively revert this to see if it fixes buildbot failures.Bob Wilson
--- Reverse-merging r99440 into '.': U test/MC/AsmParser/X86/x86_32-bit_cat.s U test/MC/AsmParser/X86/x86_32-encoding.s U include/llvm/IntrinsicsX86.td U include/llvm/CodeGen/SelectionDAGNodes.h U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
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