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2013-04-03Ensuring that both bits are set, and not just a combination of one or the other.Aaron Ballman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Cleanup PPC reciprocal-estimate functionalityHal Finkel
Incorporating review feedback from Bill Schmidt on r178617. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178672 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03R600: Factorize maximum alu per clause in a single locationVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Testing for Visual Studio 2010 SP1 or greater before calling the _xgetbv ↵Aaron Ballman
intrinsic. This also fixes a minor code formatting issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178666 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizerVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178665 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03R600: Consider KILLGT as an ALU instructionVincent Lejeune
Mesa does not override llvm behavior wrt KILLGT anymore so llvm has to handle KILLGT on its own. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Measure time that IR parsing took as part of the -time-passes measurement.Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178662 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03PPC: Enable FRES and FRSQRTE on the default PPC64 descriptionHal Finkel
I discussed this with Bill Schmidt on IRC, and it was decided that this is a safe and reasonable default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03PPC: Add a FIXME regarding the non-working fma+fneg Altivec patternHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178658 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove some obsolete PowerPC/README entriesHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03More direct types in PowerPC AltiVec intrinsics.Ulrich Weigand
This patch follows up on work done by Bill Schmidt in r178277, and replaces most of the remaining uses of VRRC in ISEL DAG patterns. The resulting .inc files are identical except for comments, so no change in code generation is expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.Bill Schmidt
For this we need to use a libcall. Previously LLVM didn't implement libcall support for frem, so I've added it in the usual straightforward manner. A test case from the bug report is included. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03AArch64: implement ETMv4 trace system registers.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Second pass at addressing PR15351 by explicitly checking for AVX supportAaron Ballman
when getting the host processor information. It emits a .byte sequence on GNUC compilers to work around lack of xgetbv support with older assemblers, and resolves a comment typo found in the previous patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178636 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Fix SRet for thiscall in i686-pc-win32Timur Iskhodzhanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03AArch64: switch patterns to be type-based rather than RegClass-basedTim Northover
It's a bit of churn in the blame log, but I think there are real benefits to the newer system so I'm making the change in one go. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Fix grammar.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove ZeroOrMore from the option description. We don't need it here.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen
The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178621 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove some unsupported-feature comments from PPC.tdHal Finkel
These refer to the reciprocal estimate support recently committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Use PPC reciprocal estimates with Newton iteration in fast-math modeHal Finkel
When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Fix the fde encoding used by mips to match gas.Rafael Espindola
This finally fixes the encoding. The patch also * Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking the wrong value. * Merge fde-reloc.s and eh-frame.s into a single test, since the only difference was the run lines. * Don't blindly test the content of the entire .eh_frame section. It makes it hard to anyone actually fixing a bug and hitting a difference in a binary blob. Instead, use a CHECK for each field and document what is being checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178615 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that ↵Aaron Ballman
doesn't understand the xgetbv instruction for some reason. Will revisit when time permits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178614 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove an optimization where we were changing an objc_autorelease into an ↵Michael Gottesman
objc_autoreleaseReturnValue. The semantics of ARC implies that a pointer passed into an objc_autorelease must live until some point (potentially down the stack) where an autorelease pool is popped. On the other hand, an objc_autoreleaseReturnValue just signifies that the object must live until the end of the given function at least. Thus objc_autorelease is stronger than objc_autoreleaseReturnValue in terms of the semantics of ARC* implying that performing the given strength reduction without any knowledge of how this relates to the autorelease pool pop that is further up the stack violates the semantics of ARC. *Even though objc_autoreleaseReturnValue if you know that no RV optimization will occur is more computationally expensive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178612 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Improved comment. No functionality change.Michael Gottesman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178605 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Attempting to fix the build on older GCC versions.Aaron Ballman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178604 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03This patch addresses PR15351 by explicitly checking for AVX supportAaron Ballman
when getting the host processor information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Formatting.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[mips] Small update to the implementation of eh.return for Mips.Akira Hatanaka
This patch initializes t9 to the handler address, but only if the relocation model is pic. This handles the case where handler to which eh.return jumps points to the start of the function. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Support and test template arguments for unions.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178586 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Reformat arguments.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178585 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.Akira Hatanaka
This patch fixes the following two tests which have been failing on llvm-mips-linux builder since r178403: LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll LLVM :: Analysis/Profiling/load-branch-weights-loops.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Allow MachineTraceMetrics to be used when the model has no resources.Jakob Stoklund Olesen
It it still possible to extract information from itineraries, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[ms-inline asm] Add support for parsing variables with namespace aliasChad Rosier
qualifiers. This patch only adds support for parsing these identifiers in the X86AsmParser. The front-end interface isn't capable of looking up these identifiers at this point in time. The end result is the compiler now errors during object file emission, rather than at parse time. Test case coming shortly. Part of rdar://13499009 and PR13340 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Fix PR15630: Replace faulty stdcx. with stwcx.Bill Schmidt
When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Don't attempt MTM heuristics without a scheduling model present.Jakob Stoklund Olesen
This should fix the PPC buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178558 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Count processor resources individually in MachineTraceMetrics.Jakob Stoklund Olesen
The new instruction scheduling models provide information about the number of cycles consumed on each processor resource. This makes it possible to estimate ILP more accurately than simply counting instructions / issue width. The functions getResourceDepth() and getResourceLength() now identify the limiting processor resource, and return a cycle count based on that. This gives more precise resource information, particularly in traces that use one resource a lot more than others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178553 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[fast-isel] Use the correct API to disable FastLowerArguments for Win64.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02DAGCombiner: Merge store/loads when we have extload/truncstoresArnold Schwaighofer
This is helps on architectures where i8,i16 are not legal but we have byte, and short loads/stores. Allowing us to merge copies like the one below on ARM. copy(char *a, char *b, int n) { do { int t0 = a[0]; int t1 = a[1]; b[0] = t0; b[1] = t1; radar://13536387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[NVPTX] Fix a few style issues in NVVMReflectJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178536 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Use a worklist to avoid a sneaky iterator invalidation.Bill Wendling
The iterator could be invalidated when it's recursively deleting a whole bunch of constant expressions in a constant initializer. Note: This was only reproducible if `opt' was run on a `.bc' file. If `opt' was run on a `.ll' file, it wouldn't crash. This is why the test first pushes the `.ll' file through `llvm-as' before feeding it to `opt'. PR15440 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add 64-bit load and store instructions.Jakob Stoklund Olesen
There is only a few new instructions, the rest is handled with patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Basic 64-bit ALU operations.Jakob Stoklund Olesen
SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Materialize 64-bit immediates.Jakob Stoklund Olesen
The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add 64-bit shift instructions.Jakob Stoklund Olesen
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add predicates for distinguishing 32-bit and 64-bit modes.Jakob Stoklund Olesen
The 'sparc' architecture produces 32-bit code while 'sparcv9' produces 64-bit code. It is also possible to run 32-bit code using SPARC v9 instructions with: llc -march=sparc -mattr=+v9 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add support for 64-bit calling convention.Jakob Stoklund Olesen
This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178523 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen
We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178522 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Fix typo in PPCISelLoweringHal Finkel
Thanks to Bill Schmidt for finding this in review of r178480. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178521 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02The divide unit is not pipeline, but it is still buffered.Andrew Trick
Buffered means a later divide may be executed out-of-order while a prior divide is sitting (buffered) in a reservation station. You can tell it's not pipelined, because operations that use it reserve it for more than one cycle: def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { let Latency = 25; let ResourceCycles = [1, 10]; } We don't currently distinguish between an unpipeline operation and one that is split into multiple micro-ops requiring the same unit. Except that the later may have NumMicroOps > 1 if they also consume issue/dispatch resources. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178519 91177308-0d34-0410-b5e6-96231b3b80d8
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