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2011-04-21In gcov profiling, give all functions an extra unified return block. This isNick Lewycky
necessary since gcov counts transitions between blocks. It can't see if you've run every line in a straight-line function, so we add an edge for it to notice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Fix think-o: emit all 8 bytes of the EOF marker. Also reflow a line in aNick Lewycky
comment for 80 columns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Add independent controls for whether GCOV profiling should emit .gcno files orNick Lewycky
instrument the program to emit .gcda. TODO: we should emit slightly different .gcda files when .gcno emission is off. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Structs have elements not parameters. I'm surprised this ever compiled...Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Add debug output for rematerializable instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Permit remat when a virtual register has multiple defs.Jakob Stoklund Olesen
TII::isTriviallyReMaterializable() shouldn't depend on any properties of the register being defined by the instruction. Rematerialization is going to create a new virtual register anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Fix another case of <rdar://problem/9184212> that only occurs with codeCameron Zwarich
generated by llvm-gcc, since llvm-gcc uses 2 i64s for passing a 4 x float vector on ARM rather than an i64 array like Clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20The bitcast case here is actually handled uniformly earlier in the function, soCameron Zwarich
delete it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129877 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Cleanup some code to better use an early return style in preparation for addingCameron Zwarich
more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Revert r129846; it's breaking a buildbot. SeeEli Friedman
http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-checks/builds/825/steps/test.llvm.stage2/logs/st.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen
On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Excise unintended hunk in 129858. <rdar://problem/7662569>Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20ARM byval support. Will be enabled by another patch to the FE. ↵Stuart Hastings
<rdar://problem/7662569> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20sys/Host: Change getHostTriple() to return the full Darwin version on OS X.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20PTX: Add intrinsics to list of built-in intrinsics, which allows them to beJustin Holewinski
used by Clang. To help Clang integration, the PTX target has been split into two targets: ptx32 and ptx64, depending on the desired pointer size. - Add GCCBuiltin class to all intrinsics - Split PTX target into ptx32 and ptx64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Behave like gnu as when a relocation crosses sections.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20ptx: add integer div and rem instructionChe-Liang Chiou
Patched by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129848 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20ptx: add floating-point comparison to setpChe-Liang Chiou
Patched by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20ptx: fix parameter orderingChe-Liang Chiou
Patched by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20This should always be signed chars, so use int8_t. This fixes a miscompile whenNick Lewycky
llvm is built with unsigned chars where an immediate such as 0xff would be zero extended to 64-bits, turning "cmp $0xff,%eax" into "cmp $0xffffffffffffffff,%eax". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Remove unused arguments.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Rewrite the expander for umulo/smulo to remember to sign extend the inputEric Christopher
manually and pass all (now) 4 arguments to the mul libcall. Add a new ExpandLibCall for just this (copied gratuitously from type legalization). Fixes rdar://9292577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Made the MC disassembler check before accessingSean Callanan
MCInst operands for ARM. This allows it to be more tolerant of malformed MCInsts or incorrect instruction metadata. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OSDaniel Dunbar
triple component. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Fix typo in the comment.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Drop support for -osx style triples, we are going with -macosxDaniel Dunbar
instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Add support for Triple::MacOSX per feedback from Chris, will removeDaniel Dunbar
Triple::OSX once Clang has moved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar
predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Add isOSDarwin() and isOSWindows() helper functions.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129815 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Fix Triple::getArchNameForAssembler to support OSX and iOSDaniel Dunbar
enumeration values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target/X86: Eliminate uses of getDarwinVers().Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target/X86: Add getTargetTriple() accessor.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target/PPC: Kill off DarwinVers, which is now dead.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target/PPC: Eliminate a use of getDarwinVers().Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target/PPC: Add a TargetTriple field.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target: Eliminate a use of getDarwinMajorNumber().Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19CodeGen: Eliminate a use of getDarwinMajorNumber().Daniel Dunbar
- There is a minor semantic change here (evidenced by the test change) for Darwin triples that have no version component. I debated changing the default behavior of isOSVersionLT, but decided it made more sense for triples to be explicit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Generalize and simplify getDarwinNumber to just be getOSVersion.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129799 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Add support for more explicit "osx" and "ios" OS names.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Delete unnecessary variable. <rdar://problem/7662569>Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129796 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Remove some duplicate op action entries and reorganize.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19This patch combines several changes from Evan Cheng for rdar://8659675.Bob Wilson
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Enable these fp vmlx codegen changes for Cortex-A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129775 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson
(and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson
Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Some single-precision VFP instructions can execute in either the VPF or NeonBob Wilson
pipelines, at least on Cortex-A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Improvements for the Cortex-A9 scheduling itineraries.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129770 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Add support for FastISel'ing varargs calls.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Force the greedy register allocator to be linked alongside linear scan.Jakob Stoklund Olesen
This means that the new register allocator can be used with 'clang -mllvm -regalloc=greedy'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129764 91177308-0d34-0410-b5e6-96231b3b80d8
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