aboutsummaryrefslogtreecommitdiff
path: root/lib
AgeCommit message (Collapse)Author
2011-08-05Remember to update LiveDebugVariables after per-block splitting.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Extract per-block splitting into its own method.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Delete getMultiUseBlocks and splitSingleBlocks.Jakob Stoklund Olesen
These functions are no longer used, and they are easily replaced with a loop calling shouldSplitSingleBlock and splitSingleBlock. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Also use shouldSplitSingleBlock() in the fallback splitting mode.Jakob Stoklund Olesen
Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go through a SmallPtrSet any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Split around single instructions to enable register class inflation.Jakob Stoklund Olesen
Normally, we don't create a live range for a single instruction in a basic block, the spiller does that anyway. However, when splitting a live range that belongs to a proper register sub-class, inserting these extra COPY instructions completely remove the constraints from the remainder interval, and it may be allocated from the larger super-class. The spiller will mop up these small live ranges if we end up spilling anyway. It calls them snippets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136989 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM load instruction shifted register index operands.Jim Grosbach
Parsing and encoding for shifted index operands for load instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM indexed load assembly parsing and encoding.Jim Grosbach
More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Detect proper register sub-classes.Jakob Stoklund Olesen
Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM refactor indexed store instructions.Jim Grosbach
Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Fix liveness computations in BranchFolding.Jakob Stoklund Olesen
The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM simplify the postidx_reg operand encoding.Jim Grosbach
The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM use a dedicated printer for postidx_reg operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Add missing register constraint for some VLD3/VLD4 pseudo instructions.Bob Wilson
<rdar://problem/9878189> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Silence unused variable warnings in release builds.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Fix http://llvm.org/bugs/show_bug.cgi?id=10583\n - test for 1 and 2 byte ↵Jason W Kim
fixups to be added git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Temporarily revert r135528 which distinguishes between two copies of oneChandler Carruth
inlined variable, based on the discussion in PR10542. This explodes the runtime of several passes down the pipeline due to a large number of "copies" remaining live across a large function. This only shows up with both debug and opt, but when it does it creates a many-minute compile when self-hosting LLVM+Clang. There are several other cases that show these types of regressions. All of this is tracked in PR10542, and progress is being made on fixing the issue. Once its addressed, the re-instated, but until then this restores the performance for self-hosting and other opt+debug builds. Devang, let me know if this causes any trouble, or impedes fixing it in any way, and thanks for working on this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix broken encodings for the Thumb2 LDRD/STRD instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04ARM assembly parsing and encoding for LDR instructions.Jim Grosbach
Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Count the total amount of stack space used in compiled functions.Jakob Stoklund Olesen
Patch by Ivan Krasin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Print DBG_VALUE variable's location info as a comment.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Increment counter inside insertDebugValue().Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04We need to map DebugLoc. It leads to Fuction * (through subprogram entry ↵Devang Patel
node) which should be appropriately mapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Linke NamedMDNodes after linking global values as comment suggests.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04allow \r's in .s files.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Introduce adjustFixupOffset that adjusts the fixup offset of a relocation.Roman Divacky
This is meant to be overriden by backends. Implement an override on PowerPC which adjusts the offset by 2 for ha16/lo16 relocation kinds. This removes a commented out hack and enables hello world to be compiled on PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Add counter.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix an obvious type. Patch by Ivan Krasin.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix an obvious type. Patch by Ivan Krasin.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04LDCL_POST and STCL_POST need one's-complement offsets, rather than two's ↵Owen Anderson
complement offsets. Add an appropriate immediate type for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Add obviously missing "break". Noticed by Andrey Karpov withDuncan Sands
the PVS-studio tool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Add an assert to check that the Addend fits the file format.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix what seems an obvious typo. Patch by Ivan Krasin. ProblemDuncan Sands
reported at http://habrahabr.ru/blogs/compilers/125626/. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Reverting r136884 updateUnloop, which crashed a linux builder.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix http://llvm.org/bugs/show_bug.cgi?id=10568Jason W Kim
Move the reloc size assert into AsmBackend - where it is more apropos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136855 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR.Bill Wendling
Fixes PR10527. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03ARM refactoring assembly parsing of memory address operands.Jim Grosbach
Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03An algorithm for incrementally updating LoopInfo within aAndrew Trick
LoopPassManager. The incremental update should be extremely cheap in most cases and can be used in places where it's not feasible to regenerate the entire loop forest. - "Unloop" is a node in the loop tree whose last backedge has been removed. - Perform reverse dataflow on the block inside Unloop to propagate the nearest loop from the block's successors. - For reducible CFG, each block in unloop is visited exactly once. This is because unloop no longer has a backedge and blocks within subloops don't change parents. - Immediate subloops are summarized by the nearest loop reachable from their exits or exits within nested subloops. - At completion the unloop blocks each have a new parent loop, and each immediate subloop has a new parent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136843 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Correctly handle multiple DBG_VALUE instructions at the same SlotIndex.Jakob Stoklund Olesen
It is possible to have multiple DBG_VALUEs for the same variable: 32L TEST32rr %vreg0<kill>, %vreg0, %EFLAGS<imp-def>; GR32:%vreg0 DBG_VALUE 2, 0, !"i" DBG_VALUE %noreg, %0, !"i" When that happens, keep the last one instead of the first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Fix broken encoding of tCBNZ.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Enable compact region splitting by default.Jakob Stoklund Olesen
This helps generate better code in functions with high register pressure. The previous version of compact region splitting caused regressions because the regions were a bit too large. A stronger negative bias applied in r136832 fixed this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Do not drop undef debug values. These are used as range termination marker ↵Devang Patel
by live debug variable pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Be more conservative when forming compact regions.Jakob Stoklund Olesen
Apply twice the negative bias on transparent blocks when computing the compact regions. This excludes loop backedges from the region when only one of the loop blocks uses the register. Previously, we would include the backedge in the region if the loop preheader and the loop latch both used the register, but the loop header didn't. When both the header and latch blocks use the register, we still keep it live on the backedge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Fix some warnings from Clang in release builds:Chandler Carruth
lib/CodeGen/RegAllocGreedy.cpp:1176:18: warning: unused variable 'B' [-Wunused-variable] if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { ^ lib/CodeGen/RegAllocGreedy.cpp:1188:18: warning: unused variable 'B' [-Wunused-variable] if (unsigned B = Cand.getBundles(BundleCand, 0)) { ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136831 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Fix typo in #include which revealed in the case-sensitive filesystem.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Remove the LowerSetJmp pass. It wasn't used effectively by any of the targets.Bill Wendling
This is some of my original LLVM code. *wipes tear* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Add more constantness in BlockFrequencyInfo.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman
platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Remove unused variables.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136803 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-06 22:59:15 +0000