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2010-10-31Revert r117876 for now, it's causing more testsuite failures.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling
looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner
Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner
and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31reapply r117858 with apparent editor malfunction fixed (somehow I Chris Lattner
got a dulicated line). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31revert r117858 while I check out a failure I missed.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31the asm matcher can't handle operands with modifiers (like ${foo:bar}).Chris Lattner
Instead of silently ignoring these instructions, emit a hard error and force the target author to either refactor the target or mark the instruction 'isCodeGenOnly'. Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are doing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner
how the push/pop mnemonic aliases are wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Factorize the duplicated logic for choosing the right argumentDuncan Sands
calling convention out of the fast and normal ISel files, and into the calling convention TD file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands
which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Add support for files with more than 65280 sections. No testcase sinceRafael Espindola
it would be a bit too big :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Make sure we have a legal type (and simple) before continuing.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner
"In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner
directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30really zap alias.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30move fcompi alias to .td file and zap some useless code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30move rep aliases to td fileChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30move sal aliases to .td file.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117821 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30fix an encoding mismatch where "sal %eax, 1" was not using the short encodingChris Lattner
for shl. Caught by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30move a bunch more aliases from .cpp -> .td file.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30move cmov aliases to .td file.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30move setcc and jcc aliases from .cpp to .tdChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30move some code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30implement (and document!) the first kind of MC assembler alias, which Chris Lattner
just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Now that the MallocInst no longer exists, this workaround forDuncan Sands
it claiming not to have side-effects is no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Add FIXME.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Clean up comments.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30If a function does a volatile load from a global constant, do notDuncan Sands
consider it to be readonly. In fact, don't even consider it to be readonly if it does a volatile load from an AllocaInst either (it is debatable as to whether readonly would be correct or not in this case; play safe for the moment). This fixes PR8279. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30stay out of the reserved namespaceChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30simplify this code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30split MaybeParseRegister into its two logical uses, eliminating malloc+free ↵Chris Lattner
traffic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Avoid re-evaluating MI.getNumOperands() every iteration of the loop.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Include MachineBasicBlock numbers in viewCFG() output.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Make sure copies are inserted after any exception handling labels at the top ofJakob Stoklund Olesen
a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117764 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is neededJakob Stoklund Olesen
elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117763 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Disable more of physical register live intervals verification.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Print out register class of spilled register.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson
There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling
conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng
defs. rdar://8610857. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Remove hard tab characters.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-2980 column fix.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach
encoder functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Fix fpscr <-> GPR latency info.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Be more strict on when we produce an undefined reference. In gas a file withRafael Espindola
just .type foo,@object will produce an undefined reference to foo. On the other hand, a file with just .weakref bar, foo will not. It is somewhat hard to support both in MC since both statements should create the symbols. It should be possible if we really need to by adding to the flags, but hopefully that is not necessary. With this patch we do not produce a undefined reference in any of those cases. The assembly file needs an actual use for the undefined reference to be present. This is in preparation for a patch implementing .weakref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Clean up indentation and other whitespace.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117728 91177308-0d34-0410-b5e6-96231b3b80d8
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