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2010-10-28Reindent.Mikhail Glushenkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng
to fail. Ugh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28- Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng
- For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng
by the number of defs first for it to match the instruction itinerary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Fix pastos in handling of AVX cvttsd2si, PR8491.Dale Johannesen
Bruno, please review, but I'm pretty sure this is right. Patch by Alex Mac! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Add correct NEON encodings for vtbl and vtbx.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add correct NEON encodings for vext, vtrn, vuzp, and vzip.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Fix compiler warnings about signed/unsigned comparisons.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Teach InstCombine not to use Add and Neg on FP. PR 8490.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Shifter ops are not always free. Do not fold them (especially to formEvan Cheng
complex load / store addressing mode) when they have higher cost and when they have more than one use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Putting r117193 back except for the compile time cost. Rather than assuming ↵Evan Cheng
fallthroughs uses all registers, just gather the union of all successor liveins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach
the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson
encoding for specifying fractional bits for fixed point conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Provide correct encodings for the get_lane and set_lane variants of vmov.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Added the x86 instruction ud2b (2nd official undefined instruction).Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27JIT imm12 encoding for constant pool entry references.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson
elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27ARM JIT fix for LDRi12 and company.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Replace pointer arithmetic with StringRef::substr.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117477 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Provide correct NEON encodings for vdup.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27x86-Win32: Switch ftol2 calling convention from stdcall to C.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27COFF: Add IMAGE_SCN_MEM_READ to text sections.Michael J. Spencer
There are currently 100 references to COFF::IMAGE_SCN in 6 files and 11 different functions. Section to attribute mapping really needs to happen in one place to avoid problems like this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Fix whitespace.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Set default type and flags for .init and .fini.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Produce an error for an invalid use of .symver.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27The new LDR* instruction patterns should handle the necessary encoding ofJim Grosbach
operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add correct NEON encodings for vsli and vsri.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add correct NEON encodings for vsra and vrsra.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27The immediate operands of an LDRi12 instruction doesn't need the addrmode2Jim Grosbach
encoding tricks. Handle the 'imm doesn't fit in the insn' case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Symbols defined as the difference of other two end up in the ABS section.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add support for the .symver directive. This is really ugly, but most of it isRafael Espindola
contained in the ELF object writer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Move more logic to isInSymtab and simplify.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-2780-col violation.Mikhail Glushenkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Remove try/catch(...) from Win32/Signals.inc.Mikhail Glushenkov
catch(...) is used in Win32/Signals.inc for catching Win32 structured exceptions, but according to [1], this is wrong. We can't simply change try/catch to __try/__finally, since this syntax is not supported by MinGW. We can use __try/__finally on MSVC and __try1/__except1 macros on MinGW [2], but I think that that solution obfuscates the code too much. The use of try/catch(...) in Signals.inc makes it impossible to link MinGW-compiled libSystem with llvm-gcc compiled executables. I propose that we just remove try/catch(...) from Signals.inc, since the meaning of the code won't change. [1] http://members.cox.net/doug_web/eh.htm [2] http://article.gmane.org/gmane.comp.compilers.llvm.cvs/81315 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Yet another tweak to X86 instructions to add ud2a as an alias to ud2Kevin Enderby
(still to add ud2b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Another tweak to X86 instructions to add the missing flex instruction (withoutKevin Enderby
the wait prefix). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Tweaks to X86 instructions to allow the 'w' suffix in places it makesKevin Enderby
sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Done differently than in r117031 that caused a valgrind error which was later reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27LDRi12 machine instructions handle negative offset operands normally (simpleJim Grosbach
integer values), not with the addrmode2 encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mcKevin Enderby
will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Handle critical loop predecessors by making both inside and outside registersJakob Stoklund Olesen
live out. This doesn't prevent us from inserting a loop preheader later on, if that is better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117424 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Compute critical loop predecessors in the same way as critical loop exits.Jakob Stoklund Olesen
Critical edges going into a loop are not as bad as critical exits. We can handle them by splitting the critical edge, or by having both inside and outside registers live out of the predecessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Physical registers trivially have multiple connected components all the time.Jakob Stoklund Olesen
Only virtuals should be requires to be connected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27One more spot where the new arm mode LDR instruction representationJim Grosbach
doesn't need the additional addrmode2 register operand. Missed it the first time around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Adding disassembler to the MicroBlaze backend.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach
rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
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