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2012-04-27X86: Don't emit conditional floating point moves on when targeting ↵Benjamin Kramer
pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27[asan] small optimization: do not emit "x+0" instructions Kostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton
the mask operand in the MCInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27Revert r155682, "Use ConstantExpr::getExtractElement when constant-folding ↵NAKAMURA Takumi
vectors" It broke stage2 build. stage1/clang sometimes crashed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27[tsan] Atomic support for ThreadSanitizer, patch by Dmitry VyukovKostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27Implement a bastardized ABI.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng
instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27Use ConstantExpr::getExtractElement when constant-folding vectorsDan Gohman
instead of getAggregateElement. This has the advantage of being more consistent and allowing higher-level constant folding to procede even if an inner extract element cannot be folded. Make ConstantFoldInstruction call ConstantFoldConstantExpression on the instruction's operands, making it more consistent with ConstantFoldConstantExpression itself. This makes sure that ConstantExprs get TargetData-aware folding before being handed off as operands for further folding. This causes more expressions to be folded, but due to a known shortcoming in constant folding, this currently has the side effect of stripping a few more nuw and inbounds flags in the non-targetdata side of constant-fold-gep.ll. This is mostly harmless. This fixes rdar://11324230. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155682 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Break up getProfitableChainIncrement().Jakob Stoklund Olesen
The required checks are moved to ChainInstruction() itself and the policy decisions are moved to IVChain::isProfitableInc(). Also cache the ExprBase in IVChain to avoid frequent recomputations. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155676 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Turn IVChain into a struct.Jakob Stoklund Olesen
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Add instcombine patterns for the following transformations:Chad Rosier
(x & y) | (x ^ y) -> x | y (x & y) + (x ^ y) -> x | y Patch by Manman Ren. rdar://10770603 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155674 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick
DAGCombine strangeness may result in multiple loads from the same offset. They both may try to glue themselves to another load. We could insist that the redundant loads glue themselves to each other, but the beter fix is to bail out from bad gluing at the time we detect it. Fixes rdar://11314175: BuildSchedUnits assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach
The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Trivial change to set UseLeaForSP flag in addition to togglingPreston Gurd
the FeatureLeaForSP feature bit when llvm auto detects Intel Atom. Patch by Andy Zhang git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26[Support/YAML] Properly fix unitialized variable warning by inserting aMichael J. Spencer
'REPLACEMENT CHARACTER' (U+FFFD) when getAsInteger fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover
On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Test commit.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to ↵Craig Topper
corei7-avx, core-avx-i, and core-avx2 cpu names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Teach the reassociate pass to fold chains of multiplies with repeatedChandler Carruth
elements to minimize the number of multiplies required to compute the final result. This uses a heuristic to attempt to form near-optimal binary exponentiation-style multiply chains. While there are some cases it misses, it seems to at least a decent job on a very diverse range of inputs. Initial benchmarks show no interesting regressions, and an 8% improvement on SPASS. Let me know if any other interesting results (in either direction) crop up! Credit to Richard Smith for the core algorithm, and helping code the patch itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng
the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Don't forget to reset 'first operand' flag when we're setting the ↵Bill Wendling
MDNodeOperand value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Print IV chain numbers while collecting them.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Remove more dead code.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Unify internal representation of ARM instructions with a register ↵Richard Barton
right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Remove the -disable-cross-class-join option.Jakob Stoklund Olesen
Cross-class joins have been normal and fully supported for a while now. With TableGen generating the getMatchingSuperRegClass() hook, they are unlikely to cause problems again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Cross-class joining is winning.Jakob Stoklund Olesen
Remove the heuristic for disabling cross-class joins. The greedy register allocator can handle the narrow register classes, and when it splits a live range, it can pick a larger register class. Benchmarks were unaffected by this change. <rdar://problem/11302212> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper
only targets that want the function get it. This prevents other targets from getting an unused function warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Use vector_shuffles instead of target specific unpack nodes for AVX ↵Craig Topper
ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Reverting r155468. Chris and Chandler have convinced me that it's dangerous andLang Hames
in poor taste. Talking through some alternate solutions with Chandler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Simplify the known retain count tracking; use a boolean state insteadDan Gohman
of a precise count. Also, move RRInfo's Partial field into PtrState, now that it won't increase the size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Build custom predecessor and successor lists for each basic block.Dan Gohman
These lists exclude invoke unwind edges and loop backedges which are being ignored. This makes it easier to ignore them consistently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach
When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Fix a naughty header include that breaks "installed" builds.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ConstantFoldSelectInstruction swapped the operands of the select.Nadav Rotem
Fix 12592. Patch by Matt Pharr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155480 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and ↵Evan Cheng
refuse to break edge to EH landing pad. rdar://11300144 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixesLang Hames
<rdar://problem/11291436>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Fix a crash on valid (if UB) bitcode that is produced for some globalChandler Carruth
constants in C++11 mode. I have no idea why it required such particular circumstances to get here, the code seems clearly to rely upon unchecked assumptions. Specifically, when we decide to form an index into a struct type, we may have gone through (at least one) zero-length array indexing round, which would have left the offset un-adjusted, and thus not necessarily valid for use when indexing the struct type. This is just an canonicalization step, so the correct thing is to refuse to canonicalize nonsensical GEPs of this form. Implemented, and test case added. Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit him with most of the debugging, and preventing me from writing the wrong code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155466 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ARM: Nuke remnant bogus code.Jim Grosbach
r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX: Add additional vbroadcast replacement sequences for integers.Nadav Rotem
Remove the v2f64 patterns because it does not match any vbroadcast instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24cmake: new fileAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: DAG builder must special case earlyclobberAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: try (not too hard) to place debug values where they belongAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: ignore debug values during schedulingAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: DAG builder support for tracking register pressure within the ↵Andrew Trick
current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24RegisterPressure: A utility for computing register pressure within aAndrew Trick
MachineInstr sequence. This uses the new target interface for tracking register pressure using pressure sets to model overlapping register classes and subregisters. RegisterPressure results can be tracked incrementally or stored at region boundaries. Global register pressure can be deduced from local RegisterPressure results if desired. This is an early, somewhat untested implementation. I'm working on testing it within the context of a register pressure reducing MachineScheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8Nadav Rotem
immediate. We can't use it here because the shuffle code does not check that the lower part of the word is identical to the upper part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton
its vector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructionsNadav Rotem
using the pattern (vbroadcast (i32load src)). In some cases, after we generate this pattern new users are added to the load node, which prevent the selection of the blend pattern. This commit provides fallback patterns which perform in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Look for the 'Is Simulated' module flag. This indicates that the program is ↵Bill Wendling
compiled to run on a simulator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155435 91177308-0d34-0410-b5e6-96231b3b80d8
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