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2012-12-17Add instruction encodings / disassembly support for 2r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings / disassembly support for 0r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Simplify assertion in XCoreInstPrinter.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Update comments to match recommended doxygen style.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Remove unnecessary include.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG ↵Craig Topper
combine don't contain an EFLAGS def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170308 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also ↵Craig Topper
add ANDN to isDefConvertible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt ↵Craig Topper
and lzcnt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Remove store forms of DEC/INC from isDefConvertible. Since they are stores ↵Craig Topper
they don't have a register def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Fix the first part of PR14478: memset now works.Chandler Carruth
PR14478 highlights a serious problem in SROA that simply wasn't being exercised due to a lack of vector input code mixed with C-library function calls. Part of SROA was written carefully to handle subvector accesses via memset and memcpy, but the rewriter never grew support for this. Fixing it required refactoring the subvector access code in other parts of SROA so it could be shared, and then fixing the splat formation logic and using subvector insertion (this patch). The PR isn't quite fixed yet, as memcpy is still broken in the same way. I'm starting on that series of patches now. Hopefully this will be enough to bring the bullet benchmark back to life with the bb-vectorizer enabled, but that may require fixing memcpy as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Extract the logic for inserting a subvector into a vector alloca.Chandler Carruth
No functionality changed. Another step of refactoring toward solving PR14487. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Lift the integer splat computation into a helper function.Chandler Carruth
No functionality changed. Refactoring leading up to the fix for PR14478 which requires some significant changes to the memset and memcpy rewriting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add debug prints for when optimizeLoadInstr folds a load.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Add instruction encodings and disassembly for 1r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Add XCore disassembler.Richard Osborne
Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Remove invalid instruction encodings.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Mark anything deriving from PseudoInstXCore as a pseudo instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170290 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Set instruction size correctly in XCoreInstrFormats.tdRichard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170289 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission.Richard Osborne
This change adds XCoreMCInstLower to do the lowering to MCInst and XCoreInstPrinter to print the MCInsts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170288 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Replace ${:comment} with the comment symbol.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16Declare class DwarfDebug before use instead of relying on a forward declarationDmitri Gribenko
from some other unrelated header. Patch by Kai. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16MCPureStreamer.cpp: Try to fix build, pruning EmitDebugLabel().NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16This patch is needed to make c++ exceptions work for mips16.Reed Kotler
Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15X86: Add a couple of target-specific dag combines that turn VSELECTS into ↵Benjamin Kramer
psubus if possible. We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases if y is a constant. DAGCombiner canonicalizes those so we first have to undo the canonicalization for those cases. The pattern occurs in gzip when the loop vectorizer is enabled. Part of PR14613. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15Relax an overly aggressive assert to fix PR14572.Chandler Carruth
The alloca width is based on the alloc size, not the type size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth
Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. Reviewed by Dan Gohman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15Revert r170246, "Enable the loop vectorizer by default."NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15This code implements most of mips16 hardfloat as it is done by gcc.Reed Kotler
In this case, essentially it is soft float with different library routines. The next step will be to make this fully interoperational with mips32 floating point and that requires creating stubs for functions with signatures that contain floating point types. I have a more sophisticated design for mips16 hardfloat which I hope to implement at a later time that directly does floating point without the need for function calls. The mips16 encoding has no floating point instructions so one needs to switch to mips32 mode to execute floating point instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15To simplify some code move the unit emission into the holders.Eric Christopher
Make emitDIE public accordingly. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15Use begin and end label names from the section for info.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby
immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Add back FoldOpIntoPhi optimizations with fix. Included test cases to help ↵Michael Ilseman
catch these errors and to test the presence of the optimization itself git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Enable the loop vectorizer by default.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170246 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14TypeLegalizer: Do not generate target specific nodes with illegal types, ↵Nadav Rotem
because we cant type-legalize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Fix a crash in ValueTracking on vectors of pointers. Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14This patch removes some nondeterminism from direct object file outputBill Schmidt
for TLS dynamic models on 64-bit PowerPC ELF. The default sort routine for relocations only sorts on the r_offset field; but with TLS, there can be two relocations with the same r_offset. For PowerPC, this patch sorts secondarily on descending r_type, which matches the behavior expected by the linker. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170237 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Add more reset methods to make all objects that the backend may use for ↵Pedro Artigas
outputting code have a reset, some are not used but were declared for completeness git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170227 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14rdar://12753946Shuxin Yang
Implement rule : "x * (select cond 1.0, 0.0) -> select cond x, 0.0" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14This patch improves the 64-bit PowerPC InitialExec TLS support by providingBill Schmidt
for a wider range of GOT entries that can hold thread-relative offsets. This matches the behavior of GCC, which was not documented in the PPC64 TLS ABI. The ABI will be updated with the new code sequence. Former sequence: ld 9,x@got@tprel(2) add 9,9,x@tls New sequence: addis 9,2,x@got@tprel@ha ld 9,x@got@tprel@l(9) add 9,9,x@tls Note that a linker optimization exists to transform the new sequence into the shorter sequence when appropriate, by replacing the addis with a nop and modifying the base register and relocation type of the ld. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Fix lint warnings in MemorySanitizer.cpp.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14[msan] Origin stores and loads do not need explicit alignment.Evgeniy Stepanov
Origin address is always 4 byte aligned, and the access type is always i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14[msan] Refactor default shadow propagation and origin tracking.Evgeniy Stepanov
This change moves the code for default shadow propagaition (handleShadowOr) and origin tracking (setOriginForNaryOp) into a new builder-like class. Also gets rid of handleShadowOrBinary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170192 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Change TargetLowering::getLoadExtAction to take an MVT, instead ofPatrik Hagglund
EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14revert r170166 - disable the loop vectorizer.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Enable the loop vectorizer.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Disable the loop vectorizer.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13Use the new MI bundling API in MachineInstrBundle itself.Jakob Stoklund Olesen
The new API is higher level than just manipulating the bundle flags directly, and the setIsInsideBundle() function will disappear soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170159 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13Remove two popcount patterns which we are already able to recognize.Shuxin Yang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170158 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13Enable the Loop Vectorizer by default for O2 and O3. Disable if-conversion ↵Nadav Rotem
by default. I plan to revert this patch later today. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13Debug Info: add support to mark member variables as artificialDavid Blaikie
This is the LLVM portion of r170154. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170156 91177308-0d34-0410-b5e6-96231b3b80d8
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