aboutsummaryrefslogtreecommitdiff
path: root/lib
AgeCommit message (Collapse)Author
2012-10-11dependence analysisSebastian Pop
Patch from Preston Briggs <preston.briggs@gmail.com>. This is an updated version of the dependence-analysis patch, including an MIV test based on Banerjee's inequalities. It's a fairly complete implementation of the paper Practical Dependence Testing Gina Goff, Ken Kennedy, and Chau-Wen Tseng PLDI 1991 It cannot yet propagate constraints between coupled RDIV subscripts (discussed in Section 5.3.2 of the paper). It's organized as a FunctionPass with a single entry point that supports testing for dependence between two instructions in a function. If there's no dependence, it returns null. If there's a dependence, it returns a pointer to a Dependence which can be queried about details (what kind of dependence, is it loop independent, direction and distance vector entries, etc). I haven't included every imaginable feature, but there's a good selection that should be adequate for supporting many loop transformations. Of course, it can be extended as necessary. Included in the patch file are many test cases, commented with C code showing the loops and array references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Follow the same routine to add target float expansion hookMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11misched: Handle "transient" non-instructions.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Don't crash when !tbaa.struct contents is invalid.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165693 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."NAKAMURA Takumi
It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Add the LLVM context to this c'tor. It will be needed in the future.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Support a common idiom on how to build an Attributes class with a single ↵Bill Wendling
attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Don't crash if a .ll file contains a forward-reference that looks like a globalNick Lewycky
value but later turns out to be a function. Unfortunately, we can't fold tests into a single file because we only get one error out of llvm-as. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165677 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add getters for the MIPS TargetTransform classesNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove unused member variable introduced in r165665.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem
information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Patch by Shuxin Yang <shuxin.llvm@gmail.com>.Nadav Rotem
Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10When generating spill and reload code for vector registers on PowerPC,Bill Schmidt
the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10The PowerPC VRSAVE register has been somewhat of an odd beast sinceBill Schmidt
the Altivec extensions were introduced. Its use is optional, and allows the compiler to communicate to the operating system which vector registers should be saved and restored during a context switch. In practice, this information is ignored by the various operating systems using the SVR4 ABI; the kernel saves and restores the entire register state. Setting the VRSAVE register is no longer performed by the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux systems. It seems best to avoid this logic within LLVM as well. This patch avoids generating code to update and restore VRSAVE for the PowerPC SVR4 ABIs (32- and 64-bit). The code remains in place for the Darwin ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add in support for expansion of all of the comparison operations to the ↵Micah Villmow
absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported. The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns: Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS) Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Revert r165652: "Remove unnecessary RTTI from the build."Sean Silva
... Apparently the RTTI is still necessary for some reason. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove unnecessary RTTI from the build.Sean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Compile TableGen without RTTI.Sean Silva
TableGen no longer needs RTTI! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Use semantically correct RTTI functions.Sean Silva
Also, some minor cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add support for FP_ROUND from v2f64 to v2f32Michael Liao
- Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add alternative support for FP_ROUND from v2f32 to v2f64Michael Liao
- Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Fix for LDRB instruction:Stepan Dyatkovskiy
SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer that described in .td. 7 ops is needed, but SDNode with only 6 is created. In more details: In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset operand is defined as am2offset_imm. am2offset_imm is complex parameter type, and actually it consists from dummy register and imm itself. As I understood trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy register was not added to SDNode, and it cause crash in Peephole Optimizer pass. The problem fixed by setting up additional dummy reg when emitting LDRB_POST_IMM instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Issue description:Stepan Dyatkovskiy
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Cleanup. Get rid of now dead code.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165613 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove the final bits of Attributes being declared in the AttributeBill Wendling
namespace. Use the attribute's enum value instead. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10My earlier "fix" for PBQP (see r165201) was incorrect. The real issue was thatLang Hames
checkRegMaskInterference only initializes the bitmask on the first interference. This fixes PR14027 and (re)fixes PR13945. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Pass into the AttributeWithIndex::get method an ArrayRef of attributeBill Wendling
enums. These are then created via the correct Attributes creation method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: fall-back to a target hook for instr bundles.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165606 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick
Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Have 'addFnAttr' take the attribute enum value. Then have it build the ↵Bill Wendling
attribute object and add it appropriately. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165595 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Reorder some parts of the td file to by in alphabetical orderReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165590 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Adding comments to clarify the reason for non-standard style in these files.Andrew Kaylor
Patch committed on behalf of Kirill Uhanov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Cosmetic changesAndrew Kaylor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10This patch adds new functions to the SectionRef and ObjectFile interfaces to ↵Andrew Kaylor
determine whether or not a section is meant to be read-only. These functions will be used by the MCJIT RuntimeDyld to give hints to the memory manager during the object loading process in a future patch. Patch by Ashok Thirumurthi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165586 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Implement MipsTargetLowering::CanLowerReturn.Akira Hatanaka
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09When expanding atomic load arith instructions, do not lose target flags. ↵Evan Cheng
rdar://12453106 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵Andrew Trick
external users of TargetSchedule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Remove LoopDependencies heuristic.Andrew Trick
This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Initial assembler implementation of Mips load address macroJack Carter
This patch provides initial implementation of load address macro instruction for Mips. We have implemented two kinds of expansions with their variations depending on the size of immediate operand: 1) load address with immediate value directly: * la d,j => addiu d,$zero,j (for -32768 <= j <= 65535) * la d,j => lui d,hi16(j) ori d,d,lo16(j) (for any other 32 bit value of j) 2) load load address with register offset value * la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535) * la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j) ori d,d,lo16(j) addu d,d,s This patch does not cover the case when the address is loaded from the value of the label or function. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Use the attribute enums to query if a function has an attribute.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Use the attribute enums to query if a parameter has an attribute.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Revert r165547 to fix build.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Use a single location for calculating the alignments.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09tblgen: Rename handleDependencies -> createDependencyFileSean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09tblgen: Move dependency file output to a separate function.Sean Silva
This keeps it out of the main flow of TableGenMain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165542 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-18 15:58:30 +0000