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2012-09-05[ms-inline asm] Add the nsdialect keyword to the lexer.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05[ms-inline asm] Emit the (new) inline asm Non-Standard Dialect attribute.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163181 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Make provenance checking conservative in cases whenDan Gohman
pointers-to-strong-pointers may be in play. These can lead to retains and releases happening in unstructured ways, foiling the optimizer. This fixes rdar://12150909. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04BypassSlowDivision: Assign to reference, don't copy the object.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Search the whole instruction for tied operands.Jakob Stoklund Olesen
Implicit uses can be dynamically tied to defs. This will soon be used for predicated instructions on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04[ms-inline asm] Add the inline assembly dialect, AsmDialect, to the InlineAsmChad Rosier
class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04[ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. ThisChad Rosier
implementation does not co-exist well with how the sideeffect and alignstack attributes are handled. The reverts r161641. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Fix my previous patch (r163164). It does now what it is supposed to do:Jakub Staszak
Doesn't set MadeChange to TRUE if BypassSlowDivision doesn't change anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163165 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Return false if BypassSlowDivision doesn't change anything.Jakub Staszak
Also a few minor changes: - use pre-inc instead of post-inc - use isa instead of dyn_cast - 80 col - trailing spaces git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Typo.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Actually use the MachineOperand field for isRegTiedToDefOperand().Jakob Stoklund Olesen
The MachineOperand::TiedTo field was maintained, but not used. This patch enables it in isRegTiedToDefOperand() and isRegTiedToUseOperand() which are the actual functions use by the register allocator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Move tie checks into MachineVerifier::visitMachineOperand.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Allow tied uses and defs in different orders.Jakob Stoklund Olesen
After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Generic Bypass Slow DivPreston Gurd
- CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Porting Hexagon MI Scheduler to the new API.Sergei Larin
Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer
This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04This patch optimizes shuffle instruction - generates 2 instructions instead ↵Elena Demikhovsky
of 4. Since this specific shuffle is widely used in many workloads we have ~10% performance on them. shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> vmovaps (%rdx), %ymm0 vshufps $8, %ymm0, %ymm0, %ymm0 vmovaps (%rcx), %ymm1 vshufps $8, %ymm0, %ymm1, %ymm1 vunpcklps %ymm0, %ymm1, %ymm0 vmovaps (%rcx), %ymm0 vmovsldup (%rdx), %ymm1 vblendps $85, %ymm0, %ymm1, %ymm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04LICM may hoist an instruction with undefined behavior above a trap.Nadav Rotem
Scan the body of the loop and find instructions that may trap. Use this information when deciding if it is safe to hoist or sink instructions. Notice that we can optimize the search of instructions that may throw in the case of nested loops. rdar://11518836 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Fix Android build of gtest and lib/Support.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Add support for fetching inlining context (stack of source code locations)Alexey Samsonov
by instruction address from DWARF. Add --inlining flag to llvm-dwarfdump to demonstrate and test this functionality, so that "llvm-dwarfdump --inlining --address=0x..." now works much like "addr2line -i 0x...", provided that the binary has debug info (Clang's -gline-tables-only *is* enough). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Be conservative about allocations that may alias the accessed pointer.Bob Wilson
If an allocation has a must-alias relation to the access pointer, we treat it as a Def. Otherwise, without this check, the code here was just skipping over the allocation call and ignoring it. I noticed this by inspection and don't have a specific testcase that it breaks, but it seems like we need to treat a may-alias allocation as a Clobber. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, addChad Rosier
the NumMCOperands argument to the GetMCInstOperandNum() function that is set to the number of MCOperands this asm operand mapped to. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Add a comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Add an interface to the GetMCInstOperandNum() function in theChad Rosier
MCTargetAsmParser class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Remove always true checks. Noticed by Adhemerval Zanella.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Add braces to the case statement.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03IRBuilderify the SjlLjEHPrepare pass.Benjamin Kramer
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163115 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03When updating live range endpoints, make sure to preserve the early clobber bit.Lang Hames
Fixs PR13719. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Fix more fallout from r158919, similar to PR13547.Bob Wilson
This code used to only handle malloc-like calls, which do not read memory. r158919 changed it to check isNoAliasFn(), which includes strdup-like and realloc-like calls, but it was not checking for dependencies on the memory read by those calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Removed unused argument.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03some peepholes that should match horizontal add/sub operations.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier
MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Move ErrorLoc decl into the scope where it's actually used.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02Fix a typo.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02Not all targets have efficient ISel code generation for select instructions.Nadav Rotem
For example, the ARM target does not have efficient ISel handling for vector selects with scalar conditions. This patch adds a TLI hook which allows the different targets to report which selects are supported well and which selects should be converted to CF duting codegen prepare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02LoopRotation: Make the brute force DomTree update more brute force.Benjamin Kramer
We update until we hit a fixpoint. This is probably slow but also slightly simplifies the code. It should also fix the occasional invalid domtrees observed when building with expensive checking. I couldn't find a case where this had a measurable slowdown, but if someone finds a pathological case where it does we may have to find a cleverer way of updating dominators here. Thanks to Duncan for the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163091 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02Rename ANDROIDEABI to Android.Logan Chien
Most of the code guarded with ANDROIDEABI are not ARM-specific, and having no relation with arm-eabi. Thus, it will be more natural to call this environment "Android" instead of "ANDROIDEABI". Note: We are not using ANDROID because several projects are using "-DANDROID" as the conditional compilation flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem
not sign-extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Only legalise a VSELECT in to bitwise operations if the vector mask bool is ↵Pete Cooper
zeros or all ones. A vector bool with just ones isn't suitable for masking with. No test case unfortunately as i couldn't find a target which fit all the conditions needed to hit this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Limit domain conversion to cases where it won't break dep chains.Tim Northover
NEON domain conversion was too heavy-handed with its widened registers, which could have stripped existing instructions of their dependency, leaving them vulnerable to scheduling errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Revert "Take account of boolean vector contents when promoting a build ↵Pete Cooper
vector from i1 to some other type. rdar://problem/12210060" This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f. Thanks to Duncan for explaining how this should have been done. Conflicts: test/CodeGen/X86/vec_select.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Fix Thumb2 fixup kind in the integrated-as.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Fix typo.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01LoopRotation: Check some invariants of the dominator updating code.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01TyposCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson
fast-math mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Fix typoMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31SelectionDAG: when constructing VZEXT_LOAD from other loads, make sure itsManman Ren
output chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://11457792 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Mark FMA4 instructions as commutable and add them to the folding tables.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()Chad Rosier
function nowadays. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163030 91177308-0d34-0410-b5e6-96231b3b80d8
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