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2012-03-20RuntimeDyldMachO has the ability to keep track ofSean Callanan
relocations (i.e., pieces of data whose addresses are referred to elsewhere in the binary image) and update the references when the section containing the relocations moves. The way this works is that there is a map from section IDs to lists of relocations. Because the relocations are associated with the section containing the data being referred to, they are updated only when the target moves. However, many data references are relative and also depend on the location of the referrer. To solve this problem, I introduced a new data structure, Referrer, which simply contains the section being referred to and the index of the relocation in that section. These referrers are associated with the source containing the reference that needs to be updated, so now regardless of which end of the relocation moves, the relocation will now be updated correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153147 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu toChad Rosier
vextractf128 with 128-bit mem dest. Combines vextractf128 $0, %ymm0, %xmm0 vmovaps %xmm0, (%rdi) to vextractf128 $0, %ymm0, (%rdi) rdar://11082570 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Assembler should accept redefinitions of unused variable symbols.Jim Grosbach
rdar://11027851 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and ↵Evan Cheng
t2PseudoExpand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20LoopSimplify bug fix. Handle indirect loop back edges.Andrew Trick
Do not call SplitBlockPredecessors on a loop preheader when one of the predecessors is an indirectbr. Otherwise, you will hit this assert: !isa<IndirectBrInst>(Preds[i]->getTerminator()) && "Cannot split an edge from an IndirectBrInst" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153133 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20LSR: teach isSimplifiedLoopNest to handle PHI IVUsers.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20LSR: fix IVUsers isSimplifiedLoopNest to perform a full domtree walkAndrew Trick
instead of skipping the current loop. My prior fix was incomplete because of an overzealous compile-time optimization: Better fix for: <rdar://problem/11049788> Segmentation fault: 11 in LoopStrengthReduce git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20remove unused variableMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to giveChad Rosier
precedence over the VINSERTF128 avx1 patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Require a base pointer for stack realignment when SP may vary dynamically.Bob Wilson
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects but not for stack adjustments around calls. Use hasReservedCallFrame() to check for both. The hasBasePointer function was already correctly checking both conditions, so the effect of this was that a base pointer would be used without checking whether the base pointer register could be reserved. I don't have a small testcase for this. <rdar://problem/11075906> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Remove some redundant checks.Bob Wilson
ARMFrameLowering::hasReservedCallFrame is already checking for variable sized objects, so there's no point in checking it twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Move the vextractf128 patterns closer to the vextractf128 def. RemoveChad Rosier
whitespace from test case. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Fix assembling ARM vst2 instructions with double-spaced registers.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20ARM non-scattered MachO relocations for movw/movt.Jim Grosbach
Needed when building -mdynamic-no-pic code. rdar://10459256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.Chad Rosier
This results in things such as vmovups 16(%rdi), %xmm0 vinsertf128 $1, %xmm0, %ymm0, %ymm0 to be combined to vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 rdar://11076953 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20The ARM instructions that have an unpredictable behavior when the pc ↵Silviu Baranga
register operand is given now fail with soft fail. Modified the regression tests to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Test Commit - add a newlineRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20It's possible to have a constant expression who's size is quite big (e.g.,Bill Wendling
i128). In that case, we may not be able to print out the MCExpr as an expression. For instance, we could have an MCExpr like this: 0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64) The MCExpr printer handles sizes up to 64-bits, but this expression would require 128-bits. In this situation, try to evaluate the constant expression and emit that as the value into 64-bit chunks. <rdar://problem/11070338> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Remove code that prevented lowering shuffles if they are used by load and ↵Craig Topper
themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Factor out target shuffle mask decoding from getShuffleScalarElt and use a ↵Craig Topper
SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper
users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Do everything up to generating code to try to get a register forEric Christopher
a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Untabify.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Add another debugging statement here.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Use lookUpRegForValue here instead of duplicating the code.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19f16 FDIV can now be legalized by promoting to f32Pete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19fix a build failure with libc++Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19ARM branch relaxation for unconditional t1 branches.Jim Grosbach
rdar://11059157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19ARM assembly, accept optional '#' on lane index number.Jim Grosbach
rdar://11057160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19[Object/COFF]: Expose getSectionContents.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19[Object/COFF]: Expose getSectionName.Michael J. Spencer
Also add some documentation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov
Patch by Weiming Zhao! This fixes PR12212 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames
instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19[asan] don't emit __asan_mapping_offset/__asan_mapping_scale by default -- ↵Kostya Serebryany
they are currently used only for experiments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd
X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Add a note for -ffast-math optimization of vector norm.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-18Factor out the multiply analysis code in ComputeMaskedBits and apply it to theNick Lewycky
overflow checking multiply intrinsic as well. Add a test for this, updating the test from grep to FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-18isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper
some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer
This is particularly helpful as both arguments tend to be constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Fix some copy and paste remnants of Cell and SPU in Hexagon files.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152981 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Fix typo in file header.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152980 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Pass TargetOptions to HexagonTargetMachine constructor by reference to match ↵Craig Topper
other targets and the base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17MC asm parser macro argument count was wrong when empty.Jim Grosbach
evaluated to '1' when the argument list was empty (should be '0'). rdar://11057257 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152967 91177308-0d34-0410-b5e6-96231b3b80d8
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