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2011-06-27Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc ↵Evan Cheng
can split live ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27indvars -disable-iv-rewrite: run RLEV after SimplifyIVUsers forAndrew Trick
a bit more control over the order SCEVs are evaluated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel
at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Calculate GetBestDestForJumpOnUndef correctly.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM Asm parsing of Thumb2 move immediate.Jim Grosbach
Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet) encode the instruction properly, but this gets the parsing part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Add exception necessitated by 133938.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM assembly carry set/clear condition code aliases for 'hi/lo'Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM assembler support for ldmfd/stmfd mnemonics.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM assembler support for vpush/vpop.Jim Grosbach
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple writeback instructions w/ SP as the base pointer. rdar://9683231 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM Assembly syntax support for arithmetic implied dest operand.Jim Grosbach
When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: sub r2, r2, #6 sub r2, #6 rdar://9682597 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27The index stored in the RegDefIter is one after the current index. When ↵Owen Anderson
getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng
into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27pre-RA-sched: Cleanup register pressure tracking.Andrew Trick
Removed the check that peeks past EXTRA_SUBREG, which I don't think makes sense any more. Intead treat it as a normal register def. No significant affect on x86 or ARM benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Track live-out physical registers in MachineDCE.Jakob Stoklund Olesen
Patch by Sanjoy Das! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Teach one piece of scalarrepl to handle lifetime markers. When transforming anNick Lewycky
alloca that only holds a copy of a global and we're going to replace the users of the alloca with that global, just nuke the lifetime intrinsics. Part of PR10121. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Move onlyUsedByLifetimeMarkers to ValueTracking so that it can be used by otherNick Lewycky
passes as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Grow the X86FloatingPoint register map to hold 16 registers.Jakob Stoklund Olesen
This allows for more live scratch registers which is needed to handle live ST registers before return and inline asm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Decode and pretty print inline asm operand descriptors.Jakob Stoklund Olesen
The INLINEASM MachineInstrs have an immediate operand describing each original inline asm operand. Decode the bits in MachineInstr::print() so it is easier to read: INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Remove unused methods.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26There is only one register coalescer. Merge it into the base class andRafael Espindola
remove the analysis group. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Merge SimpleRegisterCoalescing.cpp into RegisterCoalescer.cpp.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26merge SimpleRegisterCoalescing.h into RegisterCoalescer.h.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Move RegisterCoalescer.h to lib/CodeGen.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Remove unnecessary wrapper.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Replace dyn_cast<> with cast<> since the cast is already guarded by the ↵Chad Rosier
necessary check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25PTX: Reverting implementation of i8.Dan Bailey
The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Object: Add proper error handling.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Make Binary the parent of ObjectFile and update children to new interface.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Add Binary class. This is a cleaner parent than ObjectFile.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Add Object/Error.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Enable tail call optimization in the presence of a byval (x86-32 and x86-64).Chad Rosier
<rdar://problem/9483883> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Unbreak CMake buildDouglas Gregor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Add include guard.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Rename TargetDesc to MCTargetDescEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Refactor MachO relocation generaration into the Target directories.Jim Grosbach
Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24The scheduler needs to be aware on the existence of untyped nodes when it ↵Owen Anderson
performs type propagation for EXTRACT_SUBREG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Fix cmake build.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Fix struct member's scope. Patch by Xi Wang.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Hoist simple check above more complex checking to avoid unnecessary Chad Rosier
overheads. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Revert unintentional check-in.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Handle debug info for i128 constants.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24- Add MCRegisterInfo registration machinery. Also added x86 registration ↵Evan Cheng
routines. - Rename TargetRegisterDesc to MCRegisterDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24ARM movw/movt fixups need to mask the high bits.Jim Grosbach
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup, the upper bits need to be masked off. Previously we assumed the masking had already been done and asserted. rdar://9635991 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24tidy up whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133815 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24PTX: Add support for i8 type and introduce associated .b8 registersDan Bailey
The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier
instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24PTX: Add preliminary support for outputting debug information in the form ofJustin Holewinski
.file and .loc directives. Ideally, we would utilize the existing support in AsmPrinter for this, but I cannot find a way to get .file and .loc directives to print without the rest of the associated DWARF sections, which ptxas cannot handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Change the chain input of nodes that load the address of a function. This changeAkira Hatanaka
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a pre-existing node instead of redundantly create a new node every time it is called. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8
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